• 牛客刷题＜18＞3-8译码器

    题目：实现3-8译码器①_牛客题霸_牛客网

    知识点：Verilog中and or not的用法

    在程序模块中出现的and，or和not都是Verilog语言的保留字，由Verilog语言的原语

    规定了它们的接口顺序和用法，分别表示与门，或门，非门 

    例：

    module muxtwo（out,a,b,sl）;

    input a,b,sl;

    output out;

         not      u1(nsl,sl);   //将sl进行非运算，nsl为sl非运算后的值，u1相当于逻辑元件非门

         and  #1   u2（sela，a，nsl）;  //将a和nsl进行与运算，sela为与运算后的输出值，u2相当于逻辑元件与门

         and  #1   u3（selb，b，sl）；//将b和sl进行与运算

         or     #1   u4(out,sela,selb);  //将sela和selb进行或运算

                                                    /*#1表示输入到输出延迟1个单位时间*/

    endmodule

    解法一

    1. `timescale 1ns/1ns
    2.  
    3. module decoder_38(
    4.    input             E1_n   ,
    5.    input             E2_n   ,
    6.    input             E3     ,
    7.    input             A0     ,
    8.    input             A1     ,
    9.    input             A2     ,
    10.    
    11.    output wire       Y0_n   ,  
    12.    output wire       Y1_n   , 
    13.    output wire       Y2_n   , 
    14.    output wire       Y3_n   , 
    15.    output wire       Y4_n   , 
    16.    output wire       Y5_n   , 
    17.    output wire       Y6_n   , 
    18.    output wire       Y7_n   
    19. );
    20.     
    21.     not NO0 (A00,A0),
    22.     NO1(A10,A1),
    23.     NO2(A20,A2),
    24.     NO0_N(Y0_n,Y0),
    25.     NO1_N(Y1_n,Y1),
    26.     NO2_N(Y2_n,Y2),
    27.     NO3_N(Y3_n,Y3),
    28.     NO4_N(Y4_n,Y4),
    29.     NO5_N(Y5_n,Y5),
    30.     NO6_N(Y6_n,Y6),
    31.     NO7_N(Y7_n,Y7),
    32.     NOE1(E1,E1_n),
    33.     NOE2(E2,E2_n),
    34.     NOE3(E3,E3_n);
    35.     
    36.     and AND0(Y0,A00,A10,A20,E3,E2,E1),
    37.     AND1(Y1,A0,A10,A20,E3,E2,E1),
    38.     AND2(Y2,A00,A1,A20,E3,E2,E1),
    39.     AND3(Y3,A0,A1,A20,E3,E2,E1),
    40.     AND4(Y4,A00,A10,A2,E3,E2,E1),
    41.     AND5(Y5,A0,A10,A2,E3,E2,E1),
    42.     AND6(Y6,A00,A1,A2,E3,E2,E1),
    43.     AND7(Y7,A0,A1,A2,E3,E2,E1);
    44.  
    45. endmodule

    解法二

    1. `timescale 1ns/1ns
    2.  
    3. module decoder_38(
    4.    input             E1_n   ,
    5.    input             E2_n   ,
    6.    input             E3     ,
    7.    input             A0     ,
    8.    input             A1     ,
    9.    input             A2     ,
    10.    
    11.    output wire       Y0_n   ,  
    12.    output wire       Y1_n   , 
    13.    output wire       Y2_n   , 
    14.    output wire       Y3_n   , 
    15.    output wire       Y4_n   , 
    16.    output wire       Y5_n   , 
    17.    output wire       Y6_n   , 
    18.    output wire       Y7_n   
    19. );
    20.     
    21.     assign Y0_n = ~(({A2,A1,A0}==3'd0)&&({E3,E2_n,E1_n} ==3'b100));
    22.     assign Y1_n = ~(({A2,A1,A0}==3'd1)&&({E3,E2_n,E1_n} ==3'b100));
    23.     assign Y2_n = ~(({A2,A1,A0}==3'd2)&&({E3,E2_n,E1_n} ==3'b100));
    24.     assign Y3_n = ~(({A2,A1,A0}==3'd3)&&({E3,E2_n,E1_n} ==3'b100));
    25.     assign Y4_n = ~(({A2,A1,A0}==3'd4)&&({E3,E2_n,E1_n} ==3'b100));
    26.     assign Y5_n = ~(({A2,A1,A0}==3'd5)&&({E3,E2_n,E1_n} ==3'b100));
    27.     assign Y6_n = ~(({A2,A1,A0}==3'd6)&&({E3,E2_n,E1_n} ==3'b100));
    28.     assign Y7_n = ~(({A2,A1,A0}==3'd7)&&({E3,E2_n,E1_n} ==3'b100));
    29.  
    30. endmodule

    解法三

    1. `timescale 1ns/1ns
    2.  
    3. module decoder_38(
    4.    input             E1_n   ,
    5.    input             E2_n   ,
    6.    input             E3     ,
    7.    input             A0     ,
    8.    input             A1     ,
    9.    input             A2     ,
    10.    
    11.    output wire       Y0_n   ,  
    12.    output wire       Y1_n   , 
    13.    output wire       Y2_n   , 
    14.    output wire       Y3_n   , 
    15.    output wire       Y4_n   , 
    16.    output wire       Y5_n   , 
    17.    output wire       Y6_n   , 
    18.    output wire       Y7_n   
    19. );
    20.     
    21.     assign Y0_n = ~E3 | E2_n | E1_n | A2 | A1 | A0;
    22.     assign Y1_n = ~E3 | E2_n | E1_n | A2 | A1 | ~A0;
    23.     assign Y2_n = ~E3 | E2_n | E1_n | A2 | ~A1 | A0;
    24.     assign Y3_n = ~E3 | E2_n | E1_n | A2 | ~A1 | ~A0;
    25.     assign Y4_n = ~E3 | E2_n | E1_n | ~A2 | A1 | A0;
    26.     assign Y5_n = ~E3 | E2_n | E1_n | ~A2 | A1 | ~A0;
    27.     assign Y6_n = ~E3 | E2_n | E1_n | ~A2 | ~A1 | A0;
    28.     assign Y7_n = ~E3 | E2_n | E1_n | ~A2 | ~A1 | ~A0;
    29.     
    30. endmodule

    解法四

    1. `timescale 1ns/1ns
    2.  
    3. module decoder_38(
    4.    input             E1_n   ,
    5.    input             E2_n   ,
    6.    input             E3     ,
    7.    input             A0     ,
    8.    input             A1     ,
    9.    input             A2     ,
    10.    
    11.    output wire       Y0_n   ,  
    12.    output wire       Y1_n   , 
    13.    output wire       Y2_n   , 
    14.    output wire       Y3_n   , 
    15.    output wire       Y4_n   , 
    16.    output wire       Y5_n   , 
    17.    output wire       Y6_n   , 
    18.    output wire       Y7_n   
    19. );
    20.     wire  E;
    21.     assign E = E3 & ~E2_n & ~E1_n;
    22.     assign Y0_n = ~(E & ~A2 & ~A1 & ~A0);
    23.     assign Y1_n = ~(E & ~A2 & ~A1 &  A0);
    24.     assign Y2_n = ~(E & ~A2 &  A1 & ~A0);
    25.     assign Y3_n = ~(E & ~A2 &  A1 &  A0);
    26.     assign Y4_n = ~(E &  A2 & ~A1 & ~A0);
    27.     assign Y5_n = ~(E &  A2 & ~A1 &  A0);
    28.     assign Y6_n = ~(E &  A2 &  A1 & ~A0);
    29.     assign Y7_n = ~(E &  A2 &  A1 &  A0);
    30.     
    31. endmodule

    解法五：自己写的

    1. `timescale 1ns/1ns
    2.  
    3. module decoder_38(
    4.    input             E1_n   ,
    5.    input             E2_n   ,
    6.    input             E3     ,
    7.    input             A0     ,
    8.    input             A1     ,
    9.    input             A2     ,
    10.    
    11.    output wire       Y0_n   ,  
    12.    output wire       Y1_n   , 
    13.    output wire       Y2_n   , 
    14.    output wire       Y3_n   , 
    15.    output wire       Y4_n   , 
    16.    output wire       Y5_n   , 
    17.    output wire       Y6_n   , 
    18.    output wire       Y7_n   
    19. );
    20.     reg Y0n;
    21.     reg Y1n;
    22.     reg Y2n;
    23.     reg Y3n;
    24.     reg Y4n;
    25.     reg Y5n;
    26.     reg Y6n;
    27.     reg Y7n;
    28.     always@(*)begin
    29.         if(E3==0|E2_n==1|E1_n==1)begin
    30.             Y0n  = 1'b1;
    31.             Y1n  = 1'b1;
    32.             Y2n  = 1'b1;
    33.             Y3n  = 1'b1;
    34.             Y4n  = 1'b1;
    35.             Y5n  = 1'b1;
    36.             Y6n  = 1'b1;
    37.             Y7n  = 1'b1;
    38.         end
    39.         else begin
    40.             case({A2,A1,A0})
    41.                 3'b000:begin
    42.                    Y0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
    43.                    Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
    44.                 end
    45.                 3'b001:begin
    46.                    Y0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; 
    47.                    Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
    48.                 end
    49.                 3'b010:begin
    50.                    Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; 
    51.                    Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
    52.                 end
    53.                 3'b011:begin
    54.                    Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; 
    55.                    Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
    56.                 end
    57.                 3'b100:begin
    58.                    Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
    59.                    Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
    60.                 end
    61.                 3'b101:begin
    62.                    Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
    63.                    Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1; 
    64.                 end
    65.                 3'b110:begin
    66.                    Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
    67.                    Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1; 
    68.                 end
    69.                 3'b111:begin
    70.                    Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
    71.                    Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0; 
    72.                 end
    73.                 default:begin
    74.                    Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
    75.                    Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;  
    76.                 end
    77.             endcase
    78.         end
    79.             
    80.     end
    81.     assign  Y0_n = Y0n;
    82.     assign  Y1_n = Y1n;
    83.     assign  Y2_n = Y2n;
    84.     assign  Y3_n = Y3n;
    85.     assign  Y4_n = Y4n;
    86.     assign  Y5_n = Y5n;
    87.     assign  Y6_n = Y6n;
    88.     assign  Y7_n = Y7n;
    89.     
    90. endmodule

    Testbench

    1. `timescale 1ns/1ns
    2.  
    3. module testbench();
    4.     wire E1_n;
    5.     wire E2_n;
    6.     wire E3;
    7.     wire A0;
    8.     wire A1;
    9.     wire A2;
    10.     wire Y0_n;
    11.     wire Y1_n;
    12.     wire Y2_n;
    13.     wire Y3_n;
    14.     wire Y4_n;
    15.     wire Y5_n;
    16.     wire Y6_n;
    17.     wire Y7_n;
    18.     initial begin
    19.         $dumpfile("out.vcd");
    20.         $dumpvars(0,testbench);
    21.     end
    22.     decoder_38 inst(
    23.         .E1_n(E1_n),
    24.         .E2_n(E2_n),
    25.         .E3(E3),
    26.         .A0(A0),
    27.         .A1(A1),
    28.         .A2(A2),
    29.         .Y0_n(Y0_n),
    30.         .Y1_n(Y1_n),
    31.         .Y2_n(Y2_n),
    32.         .Y3_n(Y3_n),
    33.         .Y4_n(Y4_n),
    34.         .Y5_n(Y5_n),
    35.         .Y6_n(Y6_n),
    36.         .Y7_n(Y7_n)
    37.     );
    38. endmodule

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  • 原文地址：https://blog.csdn.net/mxh3600/article/details/126493498