Introduction to Assembly and RISC-V

1. “General Purpose” Processors

It would be highly desirable if the same hardware could execute program written in Python,Java,C or any high-level language.
It is also not sensible to execute every feature of a high-level language directly in hardware

2. Components of a Microprocessor

1. Each register is of fixed size,say 32 bits
2. The number of registers are small,say 32
3. ALU directly perform operations on the register file,typically ·x_i <- Op(x_j,x_k) where Op∈{+，AND,OR,<,>,…}
4. Memory is large,say Giga bytes,and hold program and data
5. Data can be moved back and forth between Memory and Register File using load and store instructions
   

3. Assembly Language Program

An assembly Language Program is a sequence of instructions which execute in a sequential order unless a control instruction is to be executed.
Each instruction specifies a operation supported by the processor hardware

1. ALU
2. Load and Store
3. Control Transfer:e.g. if x_i < x_j go to label l

4. Program to sum array elements

sum = a[0] + a[1] + a[2] + … + a[n-1]

x1 <- load(base) 	//load data from main memory to register x1
x2 <- load(n)    //load data from main memory to register x2
x3 <- 0                 //let register x3 = 0
loop:                   //sign for repeating
x4 <- load(Mem[x1])     //load data from main Mem[x1] to register x4
add x3, x3, x4          //ALU arithmetic:data of x3 plus data of x4 and assign the sum to regeister x3
addi x1, x1, 4          //ALU arithmetic:data of x1 plus 4 and assign the sum to regeister x1
addi x2, x2, -1         //ALU arithmetic:data of x2 plus -1 and assign the sum to regeister x2
//bnez(Branch if Not Equal to Zero)
bnez x2, loop           //if data(x2) != 0,retuen to the foregoing loop and excute again
store(sum) <- x3        //store data form register x3 to main Memory sum
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5. Instruction Set Architecture(ISA)

• ISA:The contract between software and hardware
  • Functional definition of operations and storage locations
  • Precise description of how software can invoke and access them
• RISC-V ISA:
  • A new,open,free ISA from berkeley
    

6. RISC-V Processor Storage

7. Instructions

Three Types of operations:

• Computational
• Loads and Stores
• Control Flow

register-register instructions

• 2 source operand registers
• 1 destination register
• format: oper dest,src1,src2

register-immediate instructions

• 1 source operand register
• a small constant that is encoded into the instruction
• format:oper dest,src1,const