uvm1.1从test设置uvm_config_db sequence到main_phase default_sequence时报告错误

现象1描述：

UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:

Name                   Type                    Size  Value
uvm_test_top           sw_case0                -     @463 
sw_env                 switch_env              -     @471   
agt_i                  sw_agent                -     @479 
  drv                  sw_driver               -     @622 
    rsp_port           uvm_analysis_port       -     @639 
    seq_item_port      uvm_seq_item_pull_port  -     @630 
  mon                  sw_monitor              -     @648 
    mon_ap             uvm_analysis_port       -     @658 
  sqr                  sw_sequencer            -     @499 
    rsp_export         uvm_analysis_export     -     @507 
    seq_item_export    uvm_seq_item_pull_imp   -     @613 
    arbitration_queue  array                   0     -    
    lock_queue         array                   0     -    
    num_last_reqs      integral                32    'd1  
    num_last_rsps      integral                32    'd1  
agt_o                  sw_agent                -     @487 
  mon                  sw_monitor              -     @799 
    mon_ap             uvm_analysis_port       -     @808 
  sqr                  sw_sequencer            -     @676 
    rsp_export         uvm_analysis_export     -     @684 
    seq_item_export    uvm_seq_item_pull_imp   -     @790 
    arbitration_queue  array                   0     -    
    lock_queue         array                   0     -    
    num_last_reqs      integral                32    'd1  
    num_last_rsps      integral                32    'd1  
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---

UVM_ERROR …/tc/sw_sequence0.sv(15) @ 0: uvm_test_top.sw_env.agt_i.sqr@@seq0 [SW_SEQ0] starting phase is null
Total errors:1

问题1分析：

sw_agent原始代码

function void sw_agent::connect_phase(uvm_phase phase);
super.connect_phase(phase);
mon_ap = mon.mon_ap;
endfunction

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修改后代码

function void sw_agent::connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (is_active==UVM_ACTIVE) begin
    drv.seq_item_port.connect(sqr.seq_item_export);
end
mon_ap = mon.mon_ap;
endfunction

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原因

driver和 squencer虽然内置了seq_item_port和seq_item_export，但不会自动连接，影响到了sqr下面的seq0.

现象2描述：

UVM_INFO @ 0: uvm_test_top.sw_env [CFGNRD] ::: The following resources have at least one write and no reads :::
default_sequence [/^uvm_test_top.sw_env.agt_i.sqr.main_phase$/] : (class uvm_pkg::uvm_object_wrapper) ?
但是 seq里面的transaction还是传到了drv。

问题2分析：

这个时候default_sequence还没有启动，所以写了一次，还没被读，如果加上了延时，或者在run_phase之后调用，那么就不会产生任何信息。
跟在start_of_simulation_phase中进行检查有关，如下

function void switch_env::start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
uvm_top.print_topology();
check_config_usage();
endfunction
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放在 base_test的main_phase/report_phase中进行检查，则没有 CFGNRD。