• ZYNQ之路--制作AXI4 接口IP的思路

            这篇ZYNQ之路给大家带来使用AXI总线读写DDR的介绍，此篇博客的意义在于：

    1. AXI总线基础学习
    2. PL-PS交互学习
    3. 创建带有AXI总线接口的IP核
    4. 理解AXI总线IP的移植

    PL与PS交互方式

            

             上面的图片展示了PS与PL通过接口进行交互的方式，当然除此之外PS和PL还可以通过中断等方式进行一个交互。

    AXI总线

            概述

           AXI的全称叫做“ Advanced eXtensible Interface”即高级可扩展接口，该协议是ARM公司提出的AMBA（Advanced Microcontroller Bus Architecture）3.0协议中最重要的部分，是一种面向高性能、高带宽、低延迟的片内总线。

            很容易理解这个总线的重要作用：Soc上各个子模块之间要进行通信，既然是通信那么总得有一个规范和标准，AMBA就是为了这样一个目的而提出的（不要问为啥是由ARM公司提出的，问就是因为ZYNQ使用的是ARM的内核）

            最新的AMBA（AXI4）标准

            AMBA属于不断在发展的一个架构，从前常用的诸如APB，AHB之类的总线标准，但是近些年来都统一称为AXI标准了，目前最新的AMBA标准应该是AXI4，具体包含的总线/接口请看下面的图片：

            总结，AXI协议支持以下三种接口：

    1. AXI-Full：即高性能存储映射接口。
    2. AXI-Lite：简化版的 AXI4 接口，用于较少数据量的存储映射通信，例如对模块进行配置。
    3. AXI-Stream：用于高速数据流传输，非存储映射接口，例如视频音频流传输（不能直接与PS端通信）。

            存储映射（Meamory Map）：如果一个协议是存储映射的，那么主机 所发出的会话（无论读或写）就会标明一个地址。这个地址对应于系统存储空间中的一个地址，表明是针对 该存储空间的读写操作。 

             协议细节

            首先我们来看一下AXI4总线的组成：

    AXI4总线共有五个通道：

    1. 读地址
    2. 读数据
    3. 写地址
    4. 写数据
    5. 写应答

            每个通道的基本拓扑如下：

             包含了：时钟信号（上升沿有效）、数据信号，握手信号（VALID和READY）

            AXI协议的特色或者说核心就在于：握手信号。

    • VALID信号由数据发送方发出，指示数据有效，因此一旦VALID为高电平，那么数据线上的数据就不能再改变。
    • READY信号由数据接收方发出，指示可以进行数据接收，因此READY信号只能在VALID有效之后拉高；当VALID和READY信号都有效时数据传输完成。

            之后我们再来看看五条通道的功能分配：

             

            五条通道互相独立，并且各自都遵循握手信号协议

          有关突发传输

            所谓的突发传输就是只要给定一个起始地址，一次性写入多组数据。在ZYNQ的AXI协议当中，AXI-Full协议支持最高256组数据的突发传输，而AXI-Lite一次只能传输一组数据，AXI-Stream则可以无限制地进行突发传输。

            关于突发传输的控制问题，例如突发写时主要使用WLAST信号线进行指示突发传输是否完成，最后一组数据写入完成后WLAST信号拉高（最下面三组是应答信号，由从机发出）。

    创建AXI接口的IP核

             Vivado可以使用向导创建带有AXI接口的IP模块，点击Tool里的Create and Package New IP即可打开向导。

             向导上说：这个导航将被用来完成下面的任务：

    • 打包一个新的IP（该导航将会指引你使用源文件或者你当前工程的文件等创建一个新的Vivado IP）
    • 创建一个新的AXI4外设（该导航将会指引你创建一个新的带有AXI4接口的外设，包括HDL，驱动，软件应用等等设计）

            我们选择创建一个AXI4的外设：

             下面是简单地配置AXI接口的相关信息：        我们主要目的是制作一个AXI接口的IP，因此我们选择编辑这个IP：

             下面是我们的重头戏来了：

             各位看官请移步Sources栏目，我们可以看到工程里自动多了一个顶层模块和一个实例模块，这是什么意思呢？

            这是Xilinx官方给的一个AXI接口的示例，我们设计AXI接口的IP核，如果是主接口，那么我们要有一套操控AXI接口，符合AXI时序的硬件；如果是从接口，那么我们要有能响应AXI接口请求的的一套硬件。

            从理论上来说，这些东西都是要咱们自己写的。我们原本应该仔细研读AXI接口中各个信号的时序关系，然后使用状态机让我们的功能IP能够与AXI的从机通信，或者响应主机请求。但是Xilinx官方在创建AXI接口IP的时候提供给了我们一个例子，让我们可以在这个例子的基础上进行改造。这就是向导的力量！

            顶层代码（从机）

    1.  
    2. `timescale 1 ns / 1 ps
    3.  
    4. 	module myip11_v1_0 #
    5. 	(
    6. 		// Users to add parameters here
    7.  
    8. 		// User parameters ends
    9. 		// Do not modify the parameters beyond this line
    10.  
    11.  
    12. 		// Parameters of Axi Slave Bus Interface S00_AXI
    13. 		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
    14. 		parameter integer C_S00_AXI_ADDR_WIDTH	= 4
    15. 	)
    16. 	(
    17. 		// Users to add ports here
    18.  
    19. 		// User ports ends
    20. 		// Do not modify the ports beyond this line
    21.  
    22.  
    23. 		// Ports of Axi Slave Bus Interface S00_AXI
    24. 		input wire  s00_axi_aclk,
    25. 		input wire  s00_axi_aresetn,
    26. 		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
    27. 		input wire [2 : 0] s00_axi_awprot,
    28. 		input wire  s00_axi_awvalid,
    29. 		output wire  s00_axi_awready,
    30. 		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
    31. 		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
    32. 		input wire  s00_axi_wvalid,
    33. 		output wire  s00_axi_wready,
    34. 		output wire [1 : 0] s00_axi_bresp,
    35. 		output wire  s00_axi_bvalid,
    36. 		input wire  s00_axi_bready,
    37. 		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
    38. 		input wire [2 : 0] s00_axi_arprot,
    39. 		input wire  s00_axi_arvalid,
    40. 		output wire  s00_axi_arready,
    41. 		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
    42. 		output wire [1 : 0] s00_axi_rresp,
    43. 		output wire  s00_axi_rvalid,
    44. 		input wire  s00_axi_rready
    45. 	);
    46. // Instantiation of Axi Bus Interface S00_AXI
    47. 	myip11_v1_0_S00_AXI # ( 
    48. 		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
    49. 		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
    50. 	) myip11_v1_0_S00_AXI_inst (
    51. 		.S_AXI_ACLK(s00_axi_aclk),
    52. 		.S_AXI_ARESETN(s00_axi_aresetn),
    53. 		.S_AXI_AWADDR(s00_axi_awaddr),
    54. 		.S_AXI_AWPROT(s00_axi_awprot),
    55. 		.S_AXI_AWVALID(s00_axi_awvalid),
    56. 		.S_AXI_AWREADY(s00_axi_awready),
    57. 		.S_AXI_WDATA(s00_axi_wdata),
    58. 		.S_AXI_WSTRB(s00_axi_wstrb),
    59. 		.S_AXI_WVALID(s00_axi_wvalid),
    60. 		.S_AXI_WREADY(s00_axi_wready),
    61. 		.S_AXI_BRESP(s00_axi_bresp),
    62. 		.S_AXI_BVALID(s00_axi_bvalid),
    63. 		.S_AXI_BREADY(s00_axi_bready),
    64. 		.S_AXI_ARADDR(s00_axi_araddr),
    65. 		.S_AXI_ARPROT(s00_axi_arprot),
    66. 		.S_AXI_ARVALID(s00_axi_arvalid),
    67. 		.S_AXI_ARREADY(s00_axi_arready),
    68. 		.S_AXI_RDATA(s00_axi_rdata),
    69. 		.S_AXI_RRESP(s00_axi_rresp),
    70. 		.S_AXI_RVALID(s00_axi_rvalid),
    71. 		.S_AXI_RREADY(s00_axi_rready)
    72. 	);
    73.  
    74. 	// Add user logic here
    75.  
    76. 	// User logic ends
    77.  
    78. 	endmodule

             实例代码

    1.  
    2. `timescale 1 ns / 1 ps
    3.  
    4. 	module myip11_v1_0_S00_AXI #
    5. 	(
    6. 		// Users to add parameters here
    7.  
    8. 		// User parameters ends
    9. 		// Do not modify the parameters beyond this line
    10.  
    11. 		// Width of S_AXI data bus
    12. 		parameter integer C_S_AXI_DATA_WIDTH	= 32,
    13. 		// Width of S_AXI address bus
    14. 		parameter integer C_S_AXI_ADDR_WIDTH	= 4
    15. 	)
    16. 	(
    17. 		// Users to add ports here
    18.  
    19. 		// User ports ends
    20. 		// Do not modify the ports beyond this line
    21.  
    22. 		// Global Clock Signal
    23. 		input wire  S_AXI_ACLK,
    24. 		// Global Reset Signal. This Signal is Active LOW
    25. 		input wire  S_AXI_ARESETN,
    26. 		// Write address (issued by master, acceped by Slave)
    27. 		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
    28. 		// Write channel Protection type. This signal indicates the
    29.     		// privilege and security level of the transaction, and whether
    30.     		// the transaction is a data access or an instruction access.
    31. 		input wire [2 : 0] S_AXI_AWPROT,
    32. 		// Write address valid. This signal indicates that the master signaling
    33.     		// valid write address and control information.
    34. 		input wire  S_AXI_AWVALID,
    35. 		// Write address ready. This signal indicates that the slave is ready
    36.     		// to accept an address and associated control signals.
    37. 		output wire  S_AXI_AWREADY,
    38. 		// Write data (issued by master, acceped by Slave) 
    39. 		input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
    40. 		// Write strobes. This signal indicates which byte lanes hold
    41.     		// valid data. There is one write strobe bit for each eight
    42.     		// bits of the write data bus.    
    43. 		input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
    44. 		// Write valid. This signal indicates that valid write
    45.     		// data and strobes are available.
    46. 		input wire  S_AXI_WVALID,
    47. 		// Write ready. This signal indicates that the slave
    48.     		// can accept the write data.
    49. 		output wire  S_AXI_WREADY,
    50. 		// Write response. This signal indicates the status
    51.     		// of the write transaction.
    52. 		output wire [1 : 0] S_AXI_BRESP,
    53. 		// Write response valid. This signal indicates that the channel
    54.     		// is signaling a valid write response.
    55. 		output wire  S_AXI_BVALID,
    56. 		// Response ready. This signal indicates that the master
    57.     		// can accept a write response.
    58. 		input wire  S_AXI_BREADY,
    59. 		// Read address (issued by master, acceped by Slave)
    60. 		input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
    61. 		// Protection type. This signal indicates the privilege
    62.     		// and security level of the transaction, and whether the
    63.     		// transaction is a data access or an instruction access.
    64. 		input wire [2 : 0] S_AXI_ARPROT,
    65. 		// Read address valid. This signal indicates that the channel
    66.     		// is signaling valid read address and control information.
    67. 		input wire  S_AXI_ARVALID,
    68. 		// Read address ready. This signal indicates that the slave is
    69.     		// ready to accept an address and associated control signals.
    70. 		output wire  S_AXI_ARREADY,
    71. 		// Read data (issued by slave)
    72. 		output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
    73. 		// Read response. This signal indicates the status of the
    74.     		// read transfer.
    75. 		output wire [1 : 0] S_AXI_RRESP,
    76. 		// Read valid. This signal indicates that the channel is
    77.     		// signaling the required read data.
    78. 		output wire  S_AXI_RVALID,
    79. 		// Read ready. This signal indicates that the master can
    80.     		// accept the read data and response information.
    81. 		input wire  S_AXI_RREADY
    82. 	);
    83.  
    84. 	// AXI4LITE signals
    85. 	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;
    86. 	reg  	axi_awready;
    87. 	reg  	axi_wready;
    88. 	reg [1 : 0] 	axi_bresp;
    89. 	reg  	axi_bvalid;
    90. 	reg [C_S_AXI_ADDR_WIDTH-1 : 0] 	axi_araddr;
    91. 	reg  	axi_arready;
    92. 	reg [C_S_AXI_DATA_WIDTH-1 : 0] 	axi_rdata;
    93. 	reg [1 : 0] 	axi_rresp;
    94. 	reg  	axi_rvalid;
    95.  
    96. 	// Example-specific design signals
    97. 	// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
    98. 	// ADDR_LSB is used for addressing 32/64 bit registers/memories
    99. 	// ADDR_LSB = 2 for 32 bits (n downto 2)
    100. 	// ADDR_LSB = 3 for 64 bits (n downto 3)
    101. 	localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
    102. 	localparam integer OPT_MEM_ADDR_BITS = 1;
    103. 	//----------------------------------------------
    104. 	//-- Signals for user logic register space example
    105. 	//------------------------------------------------
    106. 	//-- Number of Slave Registers 4
    107. 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg0;
    108. 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg1;
    109. 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg2;
    110. 	reg [C_S_AXI_DATA_WIDTH-1:0]	slv_reg3;
    111. 	wire	 slv_reg_rden;
    112. 	wire	 slv_reg_wren;
    113. 	reg [C_S_AXI_DATA_WIDTH-1:0]	 reg_data_out;
    114. 	integer	 byte_index;
    115. 	reg	 aw_en;
    116.  
    117. 	// I/O Connections assignments
    118.  
    119. 	assign S_AXI_AWREADY	= axi_awready;
    120. 	assign S_AXI_WREADY	= axi_wready;
    121. 	assign S_AXI_BRESP	= axi_bresp;
    122. 	assign S_AXI_BVALID	= axi_bvalid;
    123. 	assign S_AXI_ARREADY	= axi_arready;
    124. 	assign S_AXI_RDATA	= axi_rdata;
    125. 	assign S_AXI_RRESP	= axi_rresp;
    126. 	assign S_AXI_RVALID	= axi_rvalid;
    127. 	// Implement axi_awready generation
    128. 	// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
    129. 	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
    130. 	// de-asserted when reset is low.
    131.  
    132. 	always @( posedge S_AXI_ACLK )
    133. 	begin
    134. 	  if ( S_AXI_ARESETN == 1'b0 )
    135. 	    begin
    136. 	      axi_awready <= 1'b0;
    137. 	      aw_en <= 1'b1;
    138. 	    end 
    139. 	  else
    140. 	    begin    
    141. 	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
    142. 	        begin
    143. 	          // slave is ready to accept write address when 
    144. 	          // there is a valid write address and write data
    145. 	          // on the write address and data bus. This design 
    146. 	          // expects no outstanding transactions. 
    147. 	          axi_awready <= 1'b1;
    148. 	          aw_en <= 1'b0;
    149. 	        end
    150. 	        else if (S_AXI_BREADY && axi_bvalid)
    151. 	            begin
    152. 	              aw_en <= 1'b1;
    153. 	              axi_awready <= 1'b0;
    154. 	            end
    155. 	      else           
    156. 	        begin
    157. 	          axi_awready <= 1'b0;
    158. 	        end
    159. 	    end 
    160. 	end       
    161.  
    162. 	// Implement axi_awaddr latching
    163. 	// This process is used to latch the address when both 
    164. 	// S_AXI_AWVALID and S_AXI_WVALID are valid. 
    165.  
    166. 	always @( posedge S_AXI_ACLK )
    167. 	begin
    168. 	  if ( S_AXI_ARESETN == 1'b0 )
    169. 	    begin
    170. 	      axi_awaddr <= 0;
    171. 	    end 
    172. 	  else
    173. 	    begin    
    174. 	      if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
    175. 	        begin
    176. 	          // Write Address latching 
    177. 	          axi_awaddr <= S_AXI_AWADDR;
    178. 	        end
    179. 	    end 
    180. 	end       
    182. 	// Implement axi_wready generation
    183. 	// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
    184. 	// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
    185. 	// de-asserted when reset is low. 
    187. 	always @( posedge S_AXI_ACLK )
    188. 	begin
    189. 	  if ( S_AXI_ARESETN == 1'b0 )
    190. 	    begin
    191. 	      axi_wready <= 1'b0;
    192. 	    end 
    193. 	  else
    194. 	    begin    
    195. 	      if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
    196. 	        begin
    197. 	          // slave is ready to accept write data when 
    198. 	          // there is a valid write address and write data
    199. 	          // on the write address and data bus. This design 
    200. 	          // expects no outstanding transactions. 
    201. 	          axi_wready <= 1'b1;
    202. 	        end
    203. 	      else
    204. 	        begin
    205. 	          axi_wready <= 1'b0;
    206. 	        end
    207. 	    end 
    208. 	end       
    210. 	// Implement memory mapped register select and write logic generation
    211. 	// The write data is accepted and written to memory mapped registers when
    212. 	// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
    213. 	// select byte enables of slave registers while writing.
    214. 	// These registers are cleared when reset (active low) is applied.
    215. 	// Slave register write enable is asserted when valid address and data are available
    216. 	// and the slave is ready to accept the write address and write data.
    217. 	assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
    219. 	always @( posedge S_AXI_ACLK )
    220. 	begin
    221. 	  if ( S_AXI_ARESETN == 1'b0 )
    222. 	    begin
    223. 	      slv_reg0 <= 0;
    224. 	      slv_reg1 <= 0;
    225. 	      slv_reg2 <= 0;
    226. 	      slv_reg3 <= 0;
    227. 	    end 
    228. 	  else begin
    229. 	    if (slv_reg_wren)
    230. 	      begin
    231. 	        case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
    232. 	          2'h0:
    233. 	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
    234. 	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
    235. 	                // Respective byte enables are asserted as per write strobes 
    236. 	                // Slave register 0
    237. 	                slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
    238. 	              end  
    239. 	          2'h1:
    240. 	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
    241. 	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
    242. 	                // Respective byte enables are asserted as per write strobes 
    243. 	                // Slave register 1
    244. 	                slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
    245. 	              end  
    246. 	          2'h2:
    247. 	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
    248. 	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
    249. 	                // Respective byte enables are asserted as per write strobes 
    250. 	                // Slave register 2
    251. 	                slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
    252. 	              end  
    253. 	          2'h3:
    254. 	            for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
    255. 	              if ( S_AXI_WSTRB[byte_index] == 1 ) begin
    256. 	                // Respective byte enables are asserted as per write strobes 
    257. 	                // Slave register 3
    258. 	                slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
    259. 	              end  
    260. 	          default : begin
    261. 	                      slv_reg0 <= slv_reg0;
    262. 	                      slv_reg1 <= slv_reg1;
    263. 	                      slv_reg2 <= slv_reg2;
    264. 	                      slv_reg3 <= slv_reg3;
    265. 	                    end
    266. 	        endcase
    267. 	      end
    268. 	  end
    269. 	end    
    270.  
    271. 	// Implement write response logic generation
    272. 	// The write response and response valid signals are asserted by the slave 
    273. 	// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
    274. 	// This marks the acceptance of address and indicates the status of 
    275. 	// write transaction.
    276.  
    277. 	always @( posedge S_AXI_ACLK )
    278. 	begin
    279. 	  if ( S_AXI_ARESETN == 1'b0 )
    280. 	    begin
    281. 	      axi_bvalid  <= 0;
    282. 	      axi_bresp   <= 2'b0;
    283. 	    end 
    284. 	  else
    285. 	    begin    
    286. 	      if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
    287. 	        begin
    288. 	          // indicates a valid write response is available
    289. 	          axi_bvalid <= 1'b1;
    290. 	          axi_bresp  <= 2'b0; // 'OKAY' response 
    291. 	        end                   // work error responses in future
    292. 	      else
    293. 	        begin
    294. 	          if (S_AXI_BREADY && axi_bvalid) 
    295. 	            //check if bready is asserted while bvalid is high) 
    296. 	            //(there is a possibility that bready is always asserted high)   
    297. 	            begin
    298. 	              axi_bvalid <= 1'b0; 
    299. 	            end  
    300. 	        end
    301. 	    end
    302. 	end   
    304. 	// Implement axi_arready generation
    305. 	// axi_arready is asserted for one S_AXI_ACLK clock cycle when
    306. 	// S_AXI_ARVALID is asserted. axi_awready is 
    307. 	// de-asserted when reset (active low) is asserted. 
    308. 	// The read address is also latched when S_AXI_ARVALID is 
    309. 	// asserted. axi_araddr is reset to zero on reset assertion.
    311. 	always @( posedge S_AXI_ACLK )
    312. 	begin
    313. 	  if ( S_AXI_ARESETN == 1'b0 )
    314. 	    begin
    315. 	      axi_arready <= 1'b0;
    316. 	      axi_araddr  <= 32'b0;
    317. 	    end 
    318. 	  else
    319. 	    begin    
    320. 	      if (~axi_arready && S_AXI_ARVALID)
    321. 	        begin
    322. 	          // indicates that the slave has acceped the valid read address
    323. 	          axi_arready <= 1'b1;
    324. 	          // Read address latching
    325. 	          axi_araddr  <= S_AXI_ARADDR;
    326. 	        end
    327. 	      else
    328. 	        begin
    329. 	          axi_arready <= 1'b0;
    330. 	        end
    331. 	    end 
    332. 	end       
    333.  
    334. 	// Implement axi_arvalid generation
    335. 	// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
    336. 	// S_AXI_ARVALID and axi_arready are asserted. The slave registers 
    337. 	// data are available on the axi_rdata bus at this instance. The 
    338. 	// assertion of axi_rvalid marks the validity of read data on the 
    339. 	// bus and axi_rresp indicates the status of read transaction.axi_rvalid 
    340. 	// is deasserted on reset (active low). axi_rresp and axi_rdata are 
    341. 	// cleared to zero on reset (active low).  
    342. 	always @( posedge S_AXI_ACLK )
    343. 	begin
    344. 	  if ( S_AXI_ARESETN == 1'b0 )
    345. 	    begin
    346. 	      axi_rvalid <= 0;
    347. 	      axi_rresp  <= 0;
    348. 	    end 
    349. 	  else
    350. 	    begin    
    351. 	      if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
    352. 	        begin
    353. 	          // Valid read data is available at the read data bus
    354. 	          axi_rvalid <= 1'b1;
    355. 	          axi_rresp  <= 2'b0; // 'OKAY' response
    356. 	        end   
    357. 	      else if (axi_rvalid && S_AXI_RREADY)
    358. 	        begin
    359. 	          // Read data is accepted by the master
    360. 	          axi_rvalid <= 1'b0;
    361. 	        end                
    362. 	    end
    363. 	end    
    364.  
    365. 	// Implement memory mapped register select and read logic generation
    366. 	// Slave register read enable is asserted when valid address is available
    367. 	// and the slave is ready to accept the read address.
    368. 	assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
    369. 	always @(*)
    370. 	begin
    371. 	      // Address decoding for reading registers
    372. 	      case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
    373. 	        2'h0   : reg_data_out <= slv_reg0;
    374. 	        2'h1   : reg_data_out <= slv_reg1;
    375. 	        2'h2   : reg_data_out <= slv_reg2;
    376. 	        2'h3   : reg_data_out <= slv_reg3;
    377. 	        default : reg_data_out <= 0;
    378. 	      endcase
    379. 	end
    380.  
    381. 	// Output register or memory read data
    382. 	always @( posedge S_AXI_ACLK )
    383. 	begin
    384. 	  if ( S_AXI_ARESETN == 1'b0 )
    385. 	    begin
    386. 	      axi_rdata  <= 0;
    387. 	    end 
    388. 	  else
    389. 	    begin    
    390. 	      // When there is a valid read address (S_AXI_ARVALID) with 
    391. 	      // acceptance of read address by the slave (axi_arready), 
    392. 	      // output the read dada 
    393. 	      if (slv_reg_rden)
    394. 	        begin
    395. 	          axi_rdata <= reg_data_out;     // register read data
    396. 	        end   
    397. 	    end
    398. 	end    
    400. 	// Add user logic here
    402. 	// User logic ends
    404. 	endmodule

            从机的代码改造相对主机更加简单，但是想要真正学会AXI协议的IP制作，研读示例代码是必须要去做的事情。

            从机代码改造的逻辑在于寄存器：

             如图，主机会往这些寄存器里写入数据，那么这些寄存器就可以直接和我们功能模块的端口进行对接，以实现参数传递的功能。

    主机写数据--->接口实例--->寄存器-->自定义功能模块                   （数据流向）

            下一节，我想做一期 AXI-Master示例的代码解读。

  • 相关阅读:
    PeLK：101 x 101 的超大卷积网络，同参数量下反超 ViT | CVPR 2024
    找工作笔记
    两个点的距离
    最新Python深度学习技术进阶与应用
    [附源码]SSM计算机毕业设计归元种子销售管理系统JAVA
    three-tile: 三维瓦片地图框架应用示例源码-GitHub
    网络安全（补充）
    Mycat分库分表分片方式
    Java基础面试题【4】
    java毕业设计一点就到家外卖订餐系统Mybatis+系统+数据库+调试部署
  • 原文地址：https://blog.csdn.net/weixin_54358182/article/details/127041949