• 电力电子转战数字IC20220819day64——uvm实战1A

    目录

    MCDF改造

    APB接口

    验证环境的改造

    实战任务

    apb_config

    apb_master_agent

    apb_master_driver

    1.1实现apb_master_driver的drive_transfer（）

    apb_master_monitor

     1.3编写apb_master_monitor中的collect_transfer()

    apb_master_sequence_Lib

    1.2编写apb_master_sequence中的apb_master_write_seq::body()任务

    apb_master_sequencer

    slave端

    apb_slave_driver

     1.4编写apb_slave_driver的drive_response()

    apb_slave_seq_lib

    为什么要让sequence控制driver？

    这里涉及的是VIP的开发和MCDF用APB改造。

    MCDF改造

     所有的接口都发生了改变，对应在硬件中都做了修改。

    APB接口

     特点是一总（AHB或者AXI）多从，1总通过APB桥发放到后面的多从slave；2个clk完成1次W/R操作，用状态机表示为idle->setup->enable

    验证环境的改造

    由于接口几乎全部被更新，所以mcdf这一层的接口和tb的接口也需要做相应的更改。

    这里似乎没有涉及到env的问题，等下看看具体代码。

    实战任务

     

     直接看到APB部分的文件夹，可以看到文件数量大大增加，采取了`include的方式将文件分开了。

    apb_pkg只有简单的几行代码，信息都包含在别的文件中。

    1. `ifndef APB_PKG_SV
    2. `define APB_PKG_SV
    3.  
    4. package apb_pkg;
    5.  
    6. import uvm_pkg::*;
    7. `include "uvm_macros.svh"
    9. `include "apb.svh"
    10.  
    11. endpackage : apb_pkg
    12.  
    13.    
    14. `endif //  `ifndef APB_PKG_SV

    apb_pkg include了apb.svh，而后者include了主从的各个组件的sv和svh文件。

    1. `ifndef APB_SVH
    2. `define APB_SVH
    3.  
    4.  
    5. `include "apb_transfer.sv"
    6. `include "apb_config.sv"
    7.  
    8. `include "apb_master_driver.svh"
    9. `include "apb_master_monitor.svh"
    10. `include "apb_master_sequencer.svh"
    11. `include "apb_master_agent.svh"
    12.  
    13. `include "apb_slave_driver.svh"
    14. `include "apb_slave_monitor.svh"
    15. `include "apb_slave_sequencer.svh"
    16. `include "apb_slave_agent.svh"
    17.  
    18.  
    19. `include "apb_master_driver.sv"       
    20. `include "apb_master_monitor.sv"
    21. `include "apb_master_sequencer.sv"
    22. `include "apb_master_agent.sv"
    23. `include "apb_master_seq_lib.sv"
    25. `include "apb_slave_driver.sv"       
    26. `include "apb_slave_monitor.sv"
    27. `include "apb_slave_sequencer.sv"
    28. `include "apb_slave_agent.sv"
    29. `include "apb_slave_seq_lib.sv"
    30.  
    31.  
    32.  
    33.    
    34. `endif //  `ifndef APB_SVH

    在apb_tb中，include了test.svh和if.sv，要跑起仿真只需要编译pkg和tb即可（其他文件都被include了，其实也会被编译到）。tb只做了接口的配置

    1. `timescale 1ps/1ps
    2. import uvm_pkg::*;
    3. `include "uvm_macros.svh"
    4. `include "apb_tests.svh"
    5. `include "apb_if.sv"
    6. module apb_tb;
    7.   bit clk, rstn;
    8.   initial begin
    9.     fork
    10.       begin 
    11.         forever #5ns clk = !clk;
    12.       end
    13.       begin
    14.         #100ns;
    15.         rstn <= 1'b1;
    16.         #100ns;
    17.         rstn <= 1'b0;
    18.         #100ns;
    19.         rstn <= 1'b1;
    20.       end
    21.     join_none
    22.   end
    24.   apb_if intf(clk, rstn);
    26.   initial begin
    27.     uvm_config_db#(virtual apb_if)::set(uvm_root::get(), "uvm_test_top.env.mst", "vif", intf);
    28.     uvm_config_db#(virtual apb_if)::set(uvm_root::get(), "uvm_test_top.env.slv", "vif", intf);
    29.     run_test("apb_single_transaction_test");
    30.   end
    32. endmodule

    在apb_if中，包括了接口+时钟块，覆盖组covergroup。接口信号按照时序图给出，时钟块分为master和slave，信号的方向互补，monitor的时钟块所有信号都是input。

    这里又遇到覆盖率收集的问题，复习一下。定义覆盖组后再initial块中例化各个覆盖组。

    https://mp.csdn.net/mp_blog/creation/editor/125731520

    1. `ifndef APB_IF_SV
    2. `define APB_IF_SV
    3.  
    4. interface apb_if (input clk, input rstn);
    5.  
    6.   logic [31:0] paddr;
    7.   logic        pwrite;
    8.   logic        psel;
    9.   logic        penable;
    10.   logic [31:0] pwdata;
    11.   logic [31:0] prdata;
    12.  
    13.   // Control flags
    14.   bit                has_checks = 1;
    15.   bit                has_coverage = 1;
    16.  
    17.   // Actual Signals 
    18.   // USER: Add interface signals
    19.  
    20.   clocking cb_mst @(posedge clk);
    21.     // USER: Add clocking block detail
    22.     default input #1ps output #1ps;
    23.     output paddr, pwrite, psel, penable, pwdata;
    24.     input prdata;
    25.   endclocking : cb_mst
    26.  
    27.   clocking cb_slv @(posedge clk);
    28.    // USER: Add clocking block detail
    29.     default input #1ps output #1ps;
    30.     input paddr, pwrite, psel, penable, pwdata;
    31.     output prdata;
    32.   endclocking : cb_slv
    33.  
    34.   clocking cb_mon @(posedge clk);
    35.    // USER: Add clocking block detail
    36.     default input #1ps output #1ps;
    37.     input paddr, pwrite, psel, penable, pwdata, prdata;
    38.   endclocking : cb_mon
    39.  
    40.   // Coverage and assertions to be implemented here.
    41.   // USER: Add assertions/coverage here
    42.  
    43.   // APB command covergroup
    44.   covergroup cg_apb_command @(posedge clk iff rstn);
    45.     pwrite: coverpoint pwrite{
    46.       type_option.weight = 0;
    47.       bins write = {1};
    48.       bins read  = {0};
    49.  
    50.     }
    51.     psel : coverpoint psel{
    52.       type_option.weight = 0;
    53.       bins sel   = {1};
    54.       bins unsel = {0};
    55.     }
    56.     cmd  : cross pwrite, psel{
    57.       bins cmd_write = binsof(psel.sel) && binsof(pwrite.write);
    58.       bins cmd_read  = binsof(psel.sel) && binsof(pwrite.read);
    59.       bins cmd_idle  = binsof(psel.unsel);
    60.     }
    61.   endgroup
    62.  
    63.   // APB transaction timing group
    64.   covergroup cg_apb_trans_timing_group @(posedge clk iff rstn);
    65.     psel: coverpoint psel{
    66.       bins single   = (0 => 1 => 1  => 0); 
    67.       bins burst_2  = (0 => 1 [*4]  => 0); 
    68.       bins burst_4  = (0 => 1 [*8]  => 0); 
    69.       bins burst_8  = (0 => 1 [*16] => 0); 
    70.       bins burst_16 = (0 => 1 [*32] => 0); 
    71.       bins burst_32 = (0 => 1 [*64] => 0); 
    72.     }
    73.     penable: coverpoint penable {
    74.       bins single = (0 => 1 => 0 [*2:10] => 1);
    75.       bins burst  = (0 => 1 => 0         => 1);
    76.     }
    77.   endgroup
    78.  
    79.   // APB write & read order group
    80.   covergroup cg_apb_write_read_order_group @(posedge clk iff (rstn && penable));
    81.     write_read_order: coverpoint pwrite{
    82.       bins write_write = (1 => 1);
    83.       bins write_read  = (1 => 0);
    84.       bins read_write  = (0 => 1);
    85.       bins read_read   = (0 => 0);
    86.     } 
    87.   endgroup
    88.  
    89.   initial begin
    90.     automatic cg_apb_command cg0 = new();
    91.     automatic cg_apb_trans_timing_group cg1 = new();
    92.     automatic cg_apb_write_read_order_group cg2 = new();
    93.   end
    94.  
    95. endinterface : apb_if
    96.  
    97. `endif // APB_IF_SV

    关于test文件，画了个框图如下：

     接下来再逐个看各个组件

    apb_config

    这是等下用来配置agent是active还是passive用的object

    1. class apb_config extends uvm_object;
    2.  
    3.   `uvm_object_utils(apb_config)
    4.  
    5.   // USER to specify the config items
    6.   uvm_active_passive_enum  is_active = UVM_ACTIVE;
    7.   
    8.   function new (string name = "apb_config");
    9.     super.new(name);
    10.   endfunction : new
    11.  
    12.  
    13. endclass
    14.  
    15. `endif // APB_CONFIG_SV

    apb_master_agent

    由于使用了头文件，这里的方法名都要加上apb_master_agent::

    agent做了三件事：build（）例化对象，connect（）连接driver和sequencer（TLM通信，两个组件自带的seq_item_PORT）

    assign_vi配置接口

    1. //头文件
    2.  
    3. `ifndef APB_MASTER_AGENT_SVH
    4. `define APB_MASTER_AGENT_SVH
    5.  
    6. class apb_master_agent extends uvm_agent;
    7.   apb_config cfg;
    8.   apb_master_driver driver;
    9.   apb_master_sequencer sequencer;
    10.   apb_master_monitor monitor;
    11.   virtual apb_if vif;
    12.  
    13.   `uvm_component_utils_begin(apb_master_agent)
    14.     // USER: Register your fields here
    15.   `uvm_component_utils_end
    16.  
    17.   // new - constructor
    18.   extern function new (string name, uvm_component parent);
    19.  
    20.   // uvm build phase
    21.   extern function void build();
    22.  
    23.   // uvm connection phase
    24.   extern function void connect();
    25.   
    26.   // This method assigns the virtual interfaces to the agent's children
    27.   extern function void assign_vi(virtual apb_if vif);
    28. endclass : apb_master_agent
    29.  
    30. `endif // APB_MASTER_AGENT_SVH
    31.  
    32. //sv文件
    33.  
    34. `ifndef APB_MASTER_AGENT_SV
    35. `define APB_MASTER_AGENT_SV
    36. //由于使用了头文件，这里的方法名都要加上apb_master_agent::
    37. function apb_master_agent::new(string name, uvm_component parent);
    38.   super.new(name, parent);
    39. endfunction : new
    40.  
    41.  
    42. function void apb_master_agent::build();
    43.   super.build();
    44.   // get config
    45.   if( !uvm_config_db#(apb_config)::get(this,"","cfg", cfg)) begin
    46.     `uvm_warning("GETCFG","cannot get config object from config DB")
    47.      cfg = apb_config::type_id::create("cfg");
    48.   end
    49.   // get virtual interface
    50.   if( !uvm_config_db#(virtual apb_if)::get(this,"","vif", vif)) begin
    51.     `uvm_fatal("GETVIF","cannot get vif handle from config DB")
    52.   end
    53.   monitor = apb_master_monitor::type_id::create("monitor",this);
    54.   monitor.cfg = cfg;
    55.   if(cfg.is_active == UVM_ACTIVE) begin
    56.     sequencer = apb_master_sequencer::type_id::create("sequencer",this);
    57.     sequencer.cfg = cfg;
    58.     driver = apb_master_driver::type_id::create("driver",this);
    59.     driver.cfg = cfg;
    60.   end
    61. endfunction : build
    63. function void apb_master_agent::connect();
    64.   assign_vi(vif);
    65.  
    66.   if(is_active == UVM_ACTIVE) begin
    67.     driver.seq_item_port.connect(sequencer.seq_item_export);       
    68.   end
    69.  
    70. endfunction : connect
    71.   
    72. function void apb_master_agent::assign_vi(virtual apb_if vif);
    73.    monitor.vif = vif;
    74.    if (is_active == UVM_ACTIVE) begin
    75.       sequencer.vif = vif; 
    76.       driver.vif = vif; 
    77.     end
    78. endfunction : assign_vi
    79.  
    80.  
    81. `endif // APB_MASTER_AGENT_SV

    apb_master_driver

    1.  
    2. `ifndef APB_MASTER_DRIVER_SVH
    3. `define APB_MASTER_DRIVER_SVH
    4.  
    5. class apb_master_driver extends uvm_driver #(apb_transfer);
    6.   apb_config cfg;
    7.  
    8.   `uvm_component_utils_begin(apb_master_driver)
    9.  
    10.   `uvm_component_utils_end
    11.  
    12.   extern function new (string name, uvm_component parent);
    13.  
    14.   extern virtual task run();
    15.  
    16.   virtual apb_if vif;
    17.  
    18.   extern virtual protected task get_and_drive();
    19.  
    20.   extern virtual protected task drive_transfer(apb_transfer t);
    21.  
    22.   extern virtual protected task reset_listener();
    23.  
    24.   extern protected task do_idle();
    25.  
    26.   extern protected task do_write(apb_transfer t);
    27.  
    28.   extern protected task do_read(apb_transfer t);
    29.  
    30. endclass : apb_master_driver
    31.  
    32. `endif // APB_MASTER_DRIVER_SVH
    33.  
    34.

     driver的run_phase同时运行两个线程：get and drive和复位。

    而1.1就是要编写drive这个方法，对应APB的idle和读写，分别对应三个方法。在三个方法中根据时序图编写，addr和write在idle时保持不变（为了省电），时序图和代码如下。

     

     

    1.  
    2. `ifndef APB_MASTER_DRIVER_SV
    3. `define APB_MASTER_DRIVER_SV
    5. function apb_master_driver::new (string name, uvm_component parent);
    6.   super.new(name, parent);
    7. endfunction : new
    8.  
    9. task apb_master_driver::run();
    10.    fork
    11.      get_and_drive();
    12.      reset_listener();
    13.    join_none
    14. endtask : run
    16. task apb_master_driver::get_and_drive();
    17.   forever begin
    18.     seq_item_port.get_next_item(req);
    19.     `uvm_info(get_type_name(), "sequencer got next item", UVM_HIGH)
    20.     drive_transfer(req);
    21.     void'($cast(rsp, req.clone()));
    22.     rsp.set_sequence_id(req.get_sequence_id());
    23.     seq_item_port.item_done(rsp);
    24.     `uvm_info(get_type_name(), "sequencer item_done_triggered", UVM_HIGH)
    25.   end
    26. endtask : get_and_drive
    28. task apb_master_driver::drive_transfer (apb_transfer t);
    29.   `uvm_info(get_type_name(), "drive_transfer", UVM_HIGH)
    30.   case(t.trans_kind)
    31.     IDLE    : this.do_idle();
    32.     WRITE   : this.do_write(t);
    33.     READ    : this.do_read(t);
    34.     default : `uvm_error("ERRTYPE", "unrecognized transaction type")
    35.   endcase
    36. endtask : drive_transfer
    38. task apb_master_driver::do_write(apb_transfer t);
    39.   `uvm_info(get_type_name(), "do_write ...", UVM_HIGH)
    40.   @(vif.cb_mst);
    41.   vif.cb_mst.paddr <= t.addr;
    42.   vif.cb_mst.pwrite <= 1;
    43.   vif.cb_mst.psel <= 1;
    44.   vif.cb_mst.penable <= 0;
    45.   vif.cb_mst.pwdata <= t.data;
    46.   @(vif.cb_mst);
    47.   vif.cb_mst.penable <= 1;
    48.   repeat(t.idle_cycles) this.do_idle();
    49. endtask: do_write
    51. task apb_master_driver::do_read(apb_transfer t);
    52.   `uvm_info(get_type_name(), "do_write ...", UVM_HIGH)
    53.   @(vif.cb_mst);
    54.   vif.cb_mst.paddr <= t.addr;
    55.   vif.cb_mst.pwrite <= 0;
    56.   vif.cb_mst.psel <= 1;
    57.   vif.cb_mst.penable <= 0;
    58.   @(vif.cb_mst);
    59.   vif.cb_mst.penable <= 1;
    60.   #100ps;//为了采样，人为添加一个延迟，避免detal cycle
    61.   t.data = vif.prdata;
    62.   repeat(t.idle_cycles) this.do_idle();
    63. endtask: do_read
    65. task apb_master_driver::do_idle();
    66.   `uvm_info(get_type_name(), "do_idle ...", UVM_HIGH)
    67.   @(vif.cb_mst);
    68.   //vif.cb_mst.paddr <= 0;
    69.   //vif.cb_mst.pwrite <= 0;
    70.   vif.cb_mst.psel <= 0;
    71.   vif.cb_mst.penable <= 0;
    72.   vif.cb_mst.pwdata <= 0;
    73. endtask:do_idle
    75. task apb_master_driver::reset_listener();
    76.   `uvm_info(get_type_name(), "reset_listener ...", UVM_HIGH)
    77.   fork
    78.     forever begin
    79.       @(negedge vif.rstn); // ASYNC reset
    80.       vif.paddr <= 0;
    81.       vif.pwrite <= 0;
    82.       vif.psel <= 0;
    83.       vif.penable <= 0;
    84.       vif.pwdata <= 0;
    85.     end
    86.   join_none
    87. endtask
    88.  
    89. `endif // APB_MASTER_DRIVER_SV

    1.1实现apb_master_driver的drive_transfer（）

    1. task apb_master_driver::drive_transfer (apb_transfer t);
    2.   `uvm_info(get_type_name(), "drive_transfer", UVM_HIGH)
    3.   case(t.trans_kind)
    4.     IDLE    : this.do_idle();
    5.     WRITE   : this.do_write(t);
    6.     READ    : this.do_read(t);
    7.     default : `uvm_error("ERRTYPE", "unrecognized transaction type")
    8.   endcase
    9. endtask : drive_transfer
    10.  
    11. //其中apb_transfer如下，就是个item
    12.  
    13. `ifndef APB_TRANSFER_SV
    14. `define APB_TRANSFER_SV
    15. typedef enum {IDLE, WRITE, READ } apb_trans_kind;
    16.  
    17.  
    18. class apb_transfer extends uvm_sequence_item;
    19.   rand bit [31:0]      addr;
    20.   rand bit [31:0]      data;
    21.   rand apb_trans_kind  trans_kind; 
    22.   rand int idle_cycles;
    23.  
    24.   constraint cstr{
    25.     soft idle_cycles == 1;  };
    26.  
    27.   `uvm_object_utils_begin(apb_transfer)
    28.     `uvm_field_enum     (apb_trans_kind, trans_kind, UVM_ALL_ON)
    29.     `uvm_field_int      (addr, UVM_ALL_ON)
    30.     `uvm_field_int      (data, UVM_ALL_ON)
    31.     `uvm_field_int      (idle_cycles, UVM_ALL_ON)
    32.   `uvm_object_utils_end
    33.  
    34.   function new (string name = "apb_transfer_inst");
    35.     super.new(name);
    36.   endfunction : new
    37.  
    38. endclass : apb_transfer
    39.  
    40. `endif // APB_TRANSFER_SV
    41.

    再来看monitor

    apb_master_monitor

    TLM通信端口是uvm_analysis_port 

    1.  
    2. `ifndef APB_MASTER_MONITOR_SVH
    3. `define APB_MASTER_MONITOR_SVH
    4.  
    5. class apb_master_monitor extends uvm_monitor;
    6.   apb_config cfg;
    7.   bit checks_enable = 1;
    8.   bit coverage_enable = 1;
    9.   virtual apb_if vif;
    10.  
    11.   uvm_analysis_port #(apb_transfer) item_collected_port;
    12.  
    13.   `uvm_component_utils_begin(apb_master_monitor)
    14.      `uvm_field_int(checks_enable, UVM_ALL_ON)
    15.      `uvm_field_int(coverage_enable, UVM_ALL_ON)
    16.  
    17.   `uvm_component_utils_end
    18.    
    19.    extern function new(string name, uvm_component parent=null);
    20.  
    21.    extern function void build();
    22.  
    23.    extern virtual task run();
    24.  
    25.   event apb_master_cov_transaction;
    26.  
    27.   covergroup apb_master_cov_trans @apb_master_cov_transaction;
    28.  
    29.   endgroup : apb_master_cov_trans
    30.  
    31.   protected apb_transfer trans_collected;
    32.  
    33.   extern virtual protected task monitor_transactions();
    34.  
    35.   extern virtual protected task collect_transfer();
    36.  
    37.   extern protected function void perform_transfer_checks();
    38.  
    39.   extern protected function void perform_transfer_coverage();
    40.  
    41. endclass : apb_master_monitor
    42.  
    43. `endif // APB_MASTER_MONITOR_SVH
    1.  
    2. `ifndef APB_MASTER_MONITOR_SV
    3. `define APB_MASTER_MONITOR_SV
    4.  
    5. function apb_master_monitor::new(string name, uvm_component parent=null);
    6.   super.new(name, parent);
    7.   item_collected_port = new("item_collected_port",this);
    8.   trans_collected = new();
    9. endfunction:new
    10.  
    11. // build
    12. function void apb_master_monitor::build();
    13.    super.build();
    14. endfunction : build  
    15.  
    16. task apb_master_monitor::monitor_transactions();
    17.    forever begin
    18.  
    19.       // Extract data from interface into transaction
    20.       collect_transfer();
    21.  
    22.       // Check transaction
    23.       if (checks_enable)
    24.  	      perform_transfer_checks();
    25.  
    26.       // Update coverage
    27.       if (coverage_enable)
    28.  	      perform_transfer_coverage();
    29.  
    30.       // Publish to subscribers
    31.       item_collected_port.write(trans_collected);
    32.  
    33.    end
    34. endtask // monitor_transactions
    35.    
    36.  
    37. task apb_master_monitor::run();
    38.   fork
    39.     monitor_transactions();
    40.   join_none
    41. endtask // run
    42.   
    43.   
    44. task apb_master_monitor::collect_transfer();
    45.   apb_transfer t;
    46.   // Advance clock
    47.   @(vif.cb_mon);
    48.   if(vif.cb_slv.psel === 1'b1 && vif.cb_slv.penable === 1'b0) begin
    49.     t = apb_transfer::type_id::create("t");
    50.     case(vif.cb_slv.pwrite)
    51.       1'b1    : begin
    52.                   @(vif.cb_mon);//在第二个周期
    53.                   t.addr = vif.cb_mon.paddr;
    54.                   t.data = vif.cb_mon.pwdata;
    55.                   t.trans_kind = WRITE;
    56.                 end 
    57.       1'b0    : begin
    58.                   @(vif.cb_mon);
    59.                   t.addr = vif.cb_mon.paddr;
    60.                   t.data = vif.cb_mon.prdata;
    61.                   t.trans_kind = READ;
    62.                 end
    63.       default : `uvm_error(get_type_name(), "ERROR pwrite signal value")
    64.     endcase
    65.     item_collected_port.write(t);
    66.   end
    67. endtask: collect_transfer 
    68.  
    69.  
    70. // perform_transfer_checks
    71. function void apb_master_monitor::perform_transfer_checks();
    72.  
    73.  // USER: do some checks on the transfer here
    74.  
    75. endfunction : perform_transfer_checks
    76.  
    77. // perform_transfer_coverage
    78. function void apb_master_monitor::perform_transfer_coverage();
    79.  
    80.  // USER: coverage implementation
    81.   -> apb_master_cov_transaction;	
    82.  
    83. endfunction : perform_transfer_coverage
    84.  
    85. `endif // APB_MASTER_MONITOR_SV
    86.

     1.3编写apb_master_monitor中的collect_transfer()

    用于从接口获取item过来。

    在setup阶段判断是读还是写，注意！要多用一次@(vif.cb_mon)，APB在第二个周期完成读写操作

    然后把item通过analysis port的write函数写入item

    1. task apb_master_monitor::collect_transfer();
    2.   apb_transfer t;
    3.   // Advance clock
    4.   @(vif.cb_mon);
    5.   if(vif.cb_slv.psel === 1'b1 && vif.cb_slv.penable === 1'b0) begin
    6.     t = apb_transfer::type_id::create("t");
    7.     case(vif.cb_slv.pwrite)
    8.       1'b1    : begin
    9.                   @(vif.cb_mon);//在第二个周期
    10.                   t.addr = vif.cb_mon.paddr;
    11.                   t.data = vif.cb_mon.pwdata;
    12.                   t.trans_kind = WRITE;
    13.                 end 
    14.       1'b0    : begin
    15.                   @(vif.cb_mon);
    16.                   t.addr = vif.cb_mon.paddr;
    17.                   t.data = vif.cb_mon.prdata;
    18.                   t.trans_kind = READ;
    19.                 end
    20.       default : `uvm_error(get_type_name(), "ERROR pwrite signal value")
    21.     endcase
    22.     item_collected_port.write(t);
    23.   end
    24. endtask: collect_transfer

    apb_master_sequence_Lib

    包含base seq和各个seq，包括写1个，读1个，写完读1个，连续写，连续读，每次读写都需要一次`uvm_do_with，读完要把总线设为idle

    1.2编写apb_master_sequence中的apb_master_write_seq::body()任务

    base sequence只注册和例化，等待具体的子类来扩展。

    一共有5个seq，如上所示。

    single_write的body，发送一个req过去后获取一个rsp

    1.   virtual task body();
    2.     `uvm_info(get_type_name(),"Starting sequence", UVM_HIGH)
    3. 	  `uvm_do_with(req, {trans_kind == WRITE; addr == local::addr; data == local::data;})
    4.     get_response(rsp);
    5.     `uvm_info(get_type_name(),$psprintf("Done sequence: %s",req.convert2string()), UVM_HIGH)
    6.   endtask: body

    single_read的body，发送req过去后获取rsp并将rsp的data给到data，完成读出

    1.   virtual task body();
    2.     `uvm_info(get_type_name(),"Starting sequence", UVM_HIGH)
    3. 	  `uvm_do_with(req, {trans_kind == READ; addr == local::addr;})
    4.     get_response(rsp);
    5.     data = rsp.data;
    6.     `uvm_info(get_type_name(),$psprintf("Done sequence: %s",req.convert2string()), UVM_HIGH)
    7.   endtask: body

     write_read的body，写的时候要限定类型和idle_cycle，拿到rsp后读，读只限定类型和地址即可

    1.   virtual task body();
    2.     `uvm_info(get_type_name(),"Starting sequence", UVM_HIGH)
    3. 	  `uvm_do_with(req,  {trans_kind == WRITE; 
    4.                         addr == local::addr; 
    5.                         data == local::data;
    6.                         idle_cycles == local::idle_cycles;
    7.                        })
    8.     get_response(rsp);
    9.     `uvm_do_with(req, {trans_kind == READ; addr == local::addr;})
    10.     get_response(rsp);
    11.     data = rsp.data;
    12.     `uvm_info(get_type_name(),$psprintf("Done sequence: %s",req.convert2string()), UVM_HIGH)
    13.   endtask: body

     burst_write的body，写完拿到rsp后要将类型置为IDLE

    不明白为什么地址要addr == local::addr + (i<<2);

    1.   virtual task body();
    2.     `uvm_info(get_type_name(),"Starting sequence", UVM_HIGH)
    3.     foreach(data[i]) begin
    4. 	    `uvm_do_with(req, {trans_kind == WRITE; 
    5.                          addr == local::addr + (i<<2); 
    6.                          data == local::data[i];
    7.                          idle_cycles == 0;
    8.                         })
    9.       get_response(rsp);
    10.     end
    11.     `uvm_do_with(req, {trans_kind == IDLE;})
    12.     get_response(rsp);
    13.     `uvm_info(get_type_name(),$psprintf("Done sequence: %s",req.convert2string()), UVM_HIGH)
    14.   endtask: body

     burst_read的body同理。

    1.   virtual task body();
    2.     `uvm_info(get_type_name(),"Starting sequence", UVM_HIGH)
    3.     foreach(data[i]) begin
    4. 	    `uvm_do_with(req, {trans_kind == READ; 
    5.                          addr == local::addr + (i<<2); 
    6.                          idle_cycles == 0;
    7.                         })
    8.       get_response(rsp);
    9.       data[i] = rsp.data;
    10.     end
    11.     `uvm_do_with(req, {trans_kind == IDLE;})
    12.     get_response(rsp);
    13.     `uvm_info(get_type_name(),$psprintf("Done sequence: %s",req.convert2string()), UVM_HIGH)
    14.   endtask: body

    apb_master_sequencer

    只有注册和new函数例化

    slave端

    agent是一样的

    apb_slave_driver

    由于要接收master端的item，这里有个关联数组mem。

    之前的mem出现在test的base_test_sequence中，用来存放读写数据。

    与master相对应的是drive req，这里是drive_response，这也作为一个并行线程（master是两个并行线程）

    复位时要清空mem的数据，因为这边是从端

    1.  
    2. `ifndef APB_SLAVE_DRIVER_SV
    3. `define APB_SLAVE_DRIVER_SV
    4.  
    5. function apb_slave_driver::new (string name, uvm_component parent);
    6.   super.new(name, parent);
    7. endfunction : new
    8.  
    9. task apb_slave_driver::run();
    10.    fork
    11.      get_and_drive();
    12.      reset_listener();
    13.      drive_response();
    14.    join_none
    15. endtask : run
    16.  
    17. task apb_slave_driver::get_and_drive();
    18.   forever begin
    19.     seq_item_port.get_next_item(req);
    20.     `uvm_info(get_type_name(), "sequencer got next item", UVM_HIGH)
    21.     void'($cast(rsp, req.clone()));
    22.     rsp.set_sequence_id(req.get_sequence_id());
    23.     seq_item_port.item_done(rsp);
    24.     `uvm_info(get_type_name(), "sequencer item_done_triggered", UVM_HIGH)
    25.   end
    26. endtask : get_and_drive
    28. task apb_slave_driver::drive_response();
    29.   `uvm_info(get_type_name(), "drive_response", UVM_HIGH)
    30.   forever begin
    31.     @(vif.cb_slv);
    32.     if(vif.cb_slv.psel === 1'b1 && vif.cb_slv.penable === 1'b0) begin
    33.       case(vif.cb_slv.pwrite)
    34.         1'b1    : this.do_write();
    35.         1'b0    : this.do_read();
    36.         default : `uvm_error(get_type_name(), "ERROR pwrite signal value")
    37.       endcase
    38.     end
    39.     else begin
    40.       this.do_idle();
    41.     end
    42.   end
    43. endtask : drive_response
    45. task apb_slave_driver::reset_listener();
    46.   `uvm_info(get_type_name(), "reset_listener ...", UVM_HIGH)
    47.   fork
    48.     forever begin
    49.       @(negedge vif.rstn); // ASYNC reset
    50.       vif.prdata <= 0;
    51.       this.mem.delete(); // reset internal memory
    52.     end
    53.   join_none
    54. endtask: reset_listener
    56. task apb_slave_driver::do_idle();
    57.   `uvm_info(get_type_name(), "do_idle", UVM_HIGH)
    58.   vif.cb_slv.prdata <= 0;
    59. endtask: do_idle
    61. task apb_slave_driver::do_write();
    62.   bit[31:0] addr;
    63.   bit[31:0] data;
    64.   `uvm_info(get_type_name(), "do_write", UVM_HIGH)
    65.   @(vif.cb_slv);
    66.   addr = vif.cb_slv.paddr;
    67.   data = vif.cb_slv.pwdata;
    68.   mem[addr] = data;
    69. endtask: do_write
    71. task apb_slave_driver::do_read();
    72.   bit[31:0] addr;
    73.   bit[31:0] data;
    74.   `uvm_info(get_type_name(), "do_read", UVM_HIGH)
    75.   wait(vif.penable === 1'b1);
    76.   addr = vif.cb_slv.paddr;
    77.   if(mem.exists(addr))
    78.     data = mem[addr];
    79.   else
    80.     data = 0;
    81.   #1ps;
    82.   vif.prdata <= data;
    83.   @(vif.cb_slv);
    84. endtask: do_read
    85.  
    86. `endif // APB_SLAVE_DRIVER_SV

     1.4编写apb_slave_driver的drive_response()

    还是APB的状态机在setup判断是读还是写，对应读写函数。

    1. task apb_slave_driver::drive_response();
    2.   `uvm_info(get_type_name(), "drive_response", UVM_HIGH)
    3.   forever begin
    4.     @(vif.cb_slv);
    5.     if(vif.cb_slv.psel === 1'b1 && vif.cb_slv.penable === 1'b0) begin
    6.       case(vif.cb_slv.pwrite)
    7.         1'b1    : this.do_write();
    8.         1'b0    : this.do_read();
    9.         default : `uvm_error(get_type_name(), "ERROR pwrite signal value")
    10.       endcase
    11.     end
    12.     else begin
    13.       this.do_idle();
    14.     end
    15.   end
    16. endtask : drive_response

     读写函数另外编写，按照时序图给出对应的信号。

    1. task apb_slave_driver::do_idle();
    2.   `uvm_info(get_type_name(), "do_idle", UVM_HIGH)
    3.   vif.cb_slv.prdata <= 0;
    4. endtask: do_idle
    5.  
    6. task apb_slave_driver::do_write();
    7.   bit[31:0] addr;
    8.   bit[31:0] data;
    9.   `uvm_info(get_type_name(), "do_write", UVM_HIGH)
    10.   @(vif.cb_slv);
    11.   addr = vif.cb_slv.paddr;
    12.   data = vif.cb_slv.pwdata;
    13.   mem[addr] = data;
    14. endtask: do_write
    15.  
    16. task apb_slave_driver::do_read();
    17.   bit[31:0] addr;
    18.   bit[31:0] data;
    19.   `uvm_info(get_type_name(), "do_read", UVM_HIGH)
    20.   wait(vif.penable === 1'b1);
    21.   addr = vif.cb_slv.paddr;
    22.   if(mem.exists(addr))
    23.     data = mem[addr];
    24.   else
    25.     data = 0;
    26.   #1ps;
    27.   vif.prdata <= data;
    28.   @(vif.cb_slv);
    29. endtask: do_read

    apb_slave_seq_lib

    只是发送了一个item给driver，没法控制driver。

    为什么要让sequence控制driver？

    1. `ifndef APB_SLAVE_SEQ_LIB_SV
    2. `define APB_SLAVE_SEQ_LIB_SV
    3.  
    4. class example_apb_slave_seq extends uvm_sequence #(apb_transfer);
    5.  
    6.     function new(string name=""); 
    7.       super.new(name);
    8.     endfunction : new
    9.   
    10.   `uvm_object_utils(example_apb_slave_seq)    
    11.  
    12.     apb_transfer this_transfer;
    13.   
    14.     virtual task body();
    15.       `uvm_info(get_type_name(),"Starting example sequence", UVM_HIGH)
    16.        `uvm_do(this_transfer) 
    17. 	
    18.       `uvm_info(get_type_name(),$psprintf("Done example sequence: %s",this_transfer.convert2string()), UVM_HIGH)
    19.  
    20.     endtask
    21.   
    22. endclass : example_apb_slave_seq
    23.  
    24. `endif // apb_SLAVE_SEQ_LIB_SV

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  • 原文地址：https://blog.csdn.net/weixin_39668316/article/details/126410182