Verilog学习之Notgate

Create a module that implements a NOT gate.

This circuit is similar to wire, but with a slight difference. When making the connection from the wire in to the wire out we're going to implement an inverter (or "NOT-gate") instead of a plain wire.

Use an assign statement. The assign statement will continuously drive the inverse of in onto wire out.

创建一个实现非门的模块。该电路类似于电线，但略有不同。在进行从进线到出线的连接时，我们将使用逆变器（或“非门”）而不是普通线。使用分配语句。分配语句将不断地将 in 的反转驱动到线输出。

Module Declaration

module top_module( input in, output out );

Verilog has separate bitwise-NOT (~) and logical-NOT (!) operators, like C. Since we're working with a one-bit here, it doesn't matter which we choose.

Verilog 有单独的按位非 (~) 和逻辑非 (!) 运算符，就像 C 一样。由于我们在这里使用一位，所以我们选择哪个并不重要。

 

module top_module( input in, output out );
    assign out = ~in;

endmodule

module top_module( input in, output out );
    assign out = ~in;
 
endmodule