• Verilog HDL经典电路设计

    1.1 全加器的设计 

    description:example of a one-bit full add

    1. module FULLADDR(Cout,Sun,Ain,Bin,Cin);
    2. input        Ain,Bin,Cin;
    3. output       Sun,Cout;
    4.  
    5. wire         Sum;
    6. wire         Count;
    7. assign       Sum=Ain^Bin^Cin;
    8. assign       Cout=(Ain&Bin)|(Bin&Cin)|(Ain&Cin);
    9. endmodule

    1.2 数据通路

    1.2.1 四选一的多路选择器

    description:：example of a mux4-1

    1. module MUX(C,D,E,F,S,Mux_out);
    2. input             C,D,E,F,;         //input
    3. input    [1:0]    s;                //select control
    4. output            Mux_out;          //result
    5.  
    6. reg    Mux_out;                    //mux
    7. always@(C or D or E or F or S)
    8. begin
    9.         case(S)
    10.         2`b00:Mux_out=C;
    11.         2`b01:Mux_out=D;
    12.         2`b10:Mux_out=f;
    13.         default:Mux_out=S;
    14.         endcase
    15. end
    16. endmodule

    1.2.2 译码器

    description：example of 3-8decoder

    1. module DECODE(Ain,En,Yout);
    2. input                 En;            //input
    3. input     [2:0]       Ain;            //input code    
    4. output    [7:0]       Yout;            
    5.  
    6. reg        [7:0]      Yout;
    7. always@(En or Ain)
    8.     begin
    9.         if(!En)
    10.             Yout=8`0;
    11.         else
    12.             case(Ain)
    13.             3`b000:Yout=8`b0000_0001;
    14.             3`b001:Yout=8`b0000_0010;
    15.             3`b010:Yout=8`b0000_0100;
    16.             3`b011:Yout=8`b0000_1000;
    17.             3`b100:Yout=8`b0001_0000;
    18.             3`b101:Yout=8`b0010_0000;
    19.             3`b110:Yout=8`b0100_0000;
    20.             3`b111:Yout=8`b1000_0000;
    21.             default:Yout=8`b0000_0000;
    22.             endcase
    23.     end
    24. endmodule

    1.2.3 优先编码器

    description：example of Priority encoder

    1. module PRIO_ENCODE(Cin,Din,Ein,Fin,Sin,Pout);
    2. input                Cin,Din,Ein,Fin;                //input signals
    3. input      [1:0]     Sin;                            //input select contorl
    4.  
    5. output               Pout;                            //output select result
    6.  
    7. reg                  Pout;                            //Pout assignment
    8. always@(Sin or Cin or Din or Ein or Fin)
    9. begin
    10.     if(Sin==2`b00)
    11.         Pout=Cin;
    12.     else if(Sin==2`b01)
    13.         Pout=Din;
    14.     else if(Sin==2`b10)
    15.         Pout=Ein;
    16.     else
    17.         Pout=Fin;
    18. end
    19. endmodule                                             //module prio_encode

    1.3 计数器

    description：example of a counter with enable

    1. module COUNT_EN(En,Clock,Reset,Out);
    2. parameter                Width    =8;
    3. parameter                U_DLY=1;
    4. input                    Clock,Reset,En;
    5. output    [Width-1:0]    Out;
    6.  
    7. reg        [Width-1:0]    Out;
    8. always@(posedge Clock or negedge Reset)
    9.     if(!Reset)
    10.         Out<=8`b0;
    11.     else if(En)
    12.         Out<=#U_DLY Out+1;
    13. endmodule

    1.4 算术操作

    description：example of a arithmetic include +-*/

    1. module ARITHMETIC(A,B,Q1,Q2,Q3,Q4);
    2. input     [3:0]    A,B;                //input opeartor
    3. output    [4:0]    Q1;                //output sum,with carry bit
    4. output    [3:0]    Q2;                //output sutract result
    5. output    [3:0]    Q3;                //output quotion
    6. output    [7:0]    Q4;                //product
    7.  
    8. reg       [4:0]    Q1;
    9. reg       [3:0]    Q2,Q3;
    10. reg       [7:0]    Q4;                //arithmetic operate
    11.  
    12. always@(A or B)
    13.     begin
    14.         Q1=A+B;
    15.         Q2=A-B;
    16.         Q3=A/2;
    17.         Q4=A*B;
    18.     end
    19. endmodule

    1.5 逻辑操作

    description:example of a relational operate

    1. module RELATIONAL(A,B,Q1,Q2,Q3,Q4);
    2. input        [3:0]        A,b;            //operator
    3. output                    Q1,Q2,Q3,Q4;    //result
    4.  
    5. reg                        Q1,Q2,Q3,Q4;    //compare
    6.  
    7. always@(A or B)
    8.     begin
    9.         Q1=A>B;
    10.         Q2=A
    11.         Q3=A>=B;
    12.     if(A<=B)
    13.         Q4=1;
    14.     else
    15.         Q4=0;
    16.     end
    17. endmodule

    1.6 移位操作

    description:example of a shifter 

    1. module SHIFT(Data,Q1,Q2);
    2. input         [3:0]        Data;
    3. output        [3:0]        Q1,Q2;
    4.  
    5. parameter    B=2;
    6. reg          [3:0]        Q1,Q2;
    7.  
    8. always@(Data)
    9.     bagin
    10.         Q1=Data<
    11.         Q2=Data>>B;
    12.     end
    13. endmodule

    1.7 时序器件

    一个时序器件（指触发器或锁存器）就是一个一位存储器。锁存器是电平敏感存储器件，触发器是沿触发存储器件。

    触发器也称寄存器，在程序中体现为对上升沿或下降沿的探测，Verilog中如下方式表示

    （posedge Clk）——————上升沿

    （negedge Clk）——————下降沿

    下面给出不同类型触发器的描述

    1.7.1 上升沿触发的触发器

    description:example of a rising flip-flop

    1. module DFF(Data, Clk,Q);
    2. input         Data,Clk;
    3. output        Q;
    4.  
    5. reg            Q;
    6.  
    7. always@(posedge Clk)
    8.     Q    <= Data;
    9. endmodule

    1.7.2 带异步复位，上升沿触发的触发器

    description:example of a rising edge flip-flop with asynchronous reset

    1. module DFF_ASYNC_RST(Data,Clk,Rest,Q);
    2. input         Data,Clk,Reset;
    3. output        Q;
    4.  
    5. parameter    U_DLY=1;
    6.  
    7. reg           Q;
    8.  
    9. always@(posedge Clk or negedge Reset)
    10.                if(~Reset)
    11.                     Q    <=    #U_DLY 1`b0;
    12.                 else
    13.                     Q    <=    #U_DLY Data;
    14. endmodule

    1.7.3 带异步置位，上升沿触发的触发器

    description:example of a rising edge flip-flop with asynchronous preset 

    1. module DFF_ASYNC_PRE(Data,Clk,Preset,Q);
    2. input             Data,Clk,Preset;
    3. output            Q;
    4. parameter         U_DLY=1;
    5. reg               Q;
    6. always@(posedge Clk or negedge Preset)
    7.         if(~Prest)
    8.             Q    <=    #U-DLY 1`b1;
    9.         else
    10.             Q    <=    #U_CLY Data;
    11. endmodule

    1.7.4 带异步复位和置位，上升沿触发的触发器

    description:example of a rising edge flip-flop with asynchronous reset  and preset

    1. module DFF_ASYNC(Data,Clk,Reset,Prest,Q);
    2. input            Data,Clk,Reset,Preset;
    3. output           Q;
    4. parameter        U_DLY=1;
    5.  
    6. reg               Q;
    7.  
    8. always@(posedge Clk or negedge Reset or posedge Preset)
    9.     if(~Reset)
    10.         Q    <=    1`b0;
    11.     else if(Preset)
    12.         Q    <=    1`b1;
    13.      else
    14.         Q    <=    #U_DLY Data;
    15. endmodule

    1.7.5 带同步复位，上升沿触发的触发器

    description:example of a rising edge flip-flop with synchronous reset

    1. module DFF_SYNC_RST(Data,Clk,Reset,Q);
    2. input                Data,ClK,Reset;
    3. output               Q;
    4. parameter            U_DLY=1;
    5. reg                  Q;
    6. always@(posedge Clk)
    7.         if(~Reset)
    8.             Q    <=    #U_DLY 1`b0;
    9.         else
    10.             Q    <=    #U_DLY Data;
    11. endmodule

    1.7.6 带同步置位，上升沿触发的触发器

    description:example of a rising edge Flip-Flop with synchronous preset

    1. module DFF_SYNC_PRE(Data,Clk,Preset,Q);
    2. input            Data,Clk,Preset;
    3. output           Q;
    4. parameter        U_DLY=1;
    5. reg              Q;
    6. always@(posedge Clk)
    7.         if(~Preset)
    8.             Q    <=    #U_DLY 1`b1;
    9.         else
    10.             Q    <=    #U_DLY Data
    11. endmodule

    1.7.7 带异步复位和时钟使能，上升沿触发的触发器

    description:example of a Rising Edge Flip-Flop with Asynchronous Reset

    1. module DFF_CK_EN(Data,Clk,Reset,En,Q);
    2. input            Data,Clk,Reset,En;
    3. output           Q;
    4. parameter        U_DLY=1;
    5. reg              Q;
    6.  
    7. always@(posedge Clk or negedge Reset)
    8.     if(~Reset)
    9.         Q    <=    1`b0;
    10.     else if(En)
    11.         Q    <=    #U_DLY Data;
    12. endmodule

    1.8 ALU

    description:example of a 4-bit Carry Look Ahead ALU

    1. module ALU(A,B,Cin,Sum,Cout,Operate,Mode);      //input signals
    2. input         [3:0]         A,b;                //two operands of ALU
    3. input                       Cin;                //carry in at the LSB
    4. input         [3:0]         Operate;            //determine f(.) of sum=f(a,b)
    5. input                       Mode;     //arithmetic(Mode=1`b1) or logic operation(Mode=1`b0)
    6. output        [3:0]         Sum;                //result of ALU
    7. output                      Cout;               //carry produced by ALU operation
    8.  
    9. //carry generation bits and propogation bits.                                               
    10. wire          [3:0]        G,P;
    11.  
    12. //carry bits ;
    13. reg           [2:0]        C;
    14.  
    15. //funtion for carry generation:
    16. function gen
    17.     input                   A,B;
    18.     input      [1:0]        Oper;
    19.     
    20.     begin
    21.             case(Oper)
    22.                 2`b00:gen=A;
    23.                 2`b01:gen=A&B;
    24.                 2`b10:gen=A&(~B);
    25.                 2`b11:gen=1`b0;
    26.             endcase
    27.     end
    28. endfunction
    29.  
    30. //function for carry propergation:
    31. function prop
    32.     input                    A,B;
    33.     input         [1:0]      Oper;
    34.     begin
    35.         case(Oper)
    36.             2`b00:prop=1;
    37.             2`b01:prop=A|(~B);
    38.             2`b10:prop=A|B;
    39.             2`b11:prop=A;
    40.          endcase
    41.     end
    42. endfunction
    43.  
    44. //producing carry generation bits;
    45. assign G[0]=gen(A[0],B[0],Oper[1:0]);
    46. assign G[1]=gen(A[1],B[1],Oper[1:0]);
    47. assign G[2]=gen(A[2],B[2],Oper[1:0]);
    48. assign G[3]=gen(A[3],B[2],Oper[1:0]);
    49.  
    50. //producing carry  propogation bits
    51. assign P[0]=pro(A[0],B[0],Oper[3:2]);
    52. assign P[1]=Pro(A[1],B[1],Oper[3:2]);
    53. assign P[2]=Pro(A[2],B[2],Oper[3:2]);
    54. assign P[3]=Pro(A[3],B[3],Oper[3:2]);
    55.  
    56. //producing carry bits with carry-look -ahead;
    57. always@(G or P or Cin,Mode)
    58.     begin
    59.         if(Mode)begin
    60.             C[0]=G[0]|P[0] & Cin;
    61.             C[1]=G[1]|P[1] & G[0]|P[1] & P[0] & Cin;
    62.             C[2]=G[2]|P[2] & G[1]|P[2] & P[1] & G[0]|P[2] & P[1] & P[0] & Cin;
    63.             Cout=G[3]|P[3] & G[2]|P[3] & P[2] & G[1]|P[3] & P[2] & P[1] & G[0]|P[3] & P[2] & P[1] & P[0] & Cin;
    64.                  end
    65.     elsebegin
    66.         C[0]=1`b0;
    67.         C[1]=1`b0;
    68.         C[2]=1`b0;
    69.         Cout=1`b0;
    70.      end
    71.     end
    72.  
    73. //calculate the operation results;
    74. assign Sum[0]=(~G[0]&P[0])^Cin;
    75. assign Sum[1]=(~G[1]&P[1])^C[0];
    76. assign Sum[2]=(~G[2]&P[2])^C[1];
    77. assign Sum[3]=(~G[3]&P[3])^C[2];
    78. endmodule

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  • 原文地址：https://blog.csdn.net/m0_61687959/article/details/125806542