xilinx reset，data同步

用于从一个时钟域跨越到另一个时钟域的信号，这是一个多触发器流水线，所有触发器一起放入同一个切片中。 因此，两者之间的路由延迟最小，以防止亚稳态问题。

//------------------------------------------------------------------------------
// Title      : Reset Sync Block
// Project    : 10G Gigabit Ethernet
//------------------------------------------------------------------------------
// File       : axi_10g_ethernet_0_sync_reset.v
// Author     : Xilinx Inc.
//------------------------------------------------------------------------------
// Description: Used on signals crossing from one clock domain to another, this
//              is a multiple flip-flop pipeline, with all flops placed together
//              into the same slice.  Thus the routing delay between the two is
//              minimum to safe-guar
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