HDLBits-Fsm1

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1s, but using asynchronous reset.

Module Declaration

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);

自己写的代码：

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);
    reg[0:0] state;  //存储状态
    // out 作为输出
    parameter  A = 1'b0 ,
               B = 1'b1;
    always @(posedge clk or posedge areset) begin
        if(areset)begin 
            state <= B;
            out <= 1'b1;
        end
        else begin 
            case(state)
                B: if(in==1'b0)begin 
                    state <= A;
                    out <= 1'b0;
                end
                    else begin 
                        state <= B;
                        out <= 1'b1;
                    end
                A: if(in==1'b1)begin 
                    state <= A;
                    out <= 1'b0;
                end
                    else begin 
                        state <= B;
                        out <= 1'b1;
                    end
            endcase
        end
    end
endmodule

异步areset 可以通过always @(posedge clk or posedge areset) 来完成。

参考代码：

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  
 
    parameter A=1'd0, B=1'd1; 
    reg state, next_state;
 
    always @(*) begin    // This is a combinational always block
        // State transition logic
        case(state)
            A:next_state = (in)?A:B;
            B:next_state = (in)?B:A;
        endcase
    end
 
    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)begin
            state<=B;
        end
        else begin
            state<=next_state;
        end
    end
 
    // Output logic
    assign out = (state == B);
 
endmodule

该代码将状态转换逻辑单独写成了一个组合逻辑