• Xilinx FPGA:vivado用串口控制数码管

    一、项目要求

          要求输入从千位到个位数字给4位数码管，要求分别输入的数字都能显示

    二、关键信号流向

    三、程序设计

    顶层：

    1. `timescale 1ns / 1ps
    2. module TOP(
    3.     input                sys_clk   ,
    4.     input                rst_n     ,
    5.     input                rx_data  ,
    6.     output wire[3:0]    DIG       ,
    7.     output wire[7:0]    SEG       
    8.     );
    9.     
    10.     /接收端模块例化
    11.     wire [7:0]        uart_data   ;
    12.     wire              rx_done     ;
    13.     uart_rx  uart_rx_u1(
    14.                      .   sys_clk   (sys_clk  )    ,
    15.                      .   rst_n     (rst_n    )    ,
    16.                      .   rx_data   (rx_data  )    ,
    17.                      .   uart_data (uart_data)    ,
    18.                      .   rx_done   (rx_done  )
    19.  
    20.     );
    21.     
    22.     //translate模块例化
    23.     wire[7:0]          trans_data   ;
    24.     translate translate_u1(
    25.                       .  sys_clk    (sys_clk   )   ,
    26.                       .  rst_n      (rst_n     )   ,
    27.                       .  uart_data  (uart_data )   ,
    28.                       .  rx_done    (rx_done   )   ,
    29.                       .  trans_data (trans_data)
    30.  
    31.         );
    32.     
    33.     //conversion模块例化
    34.       wire[15:0]        number   ;
    35.     conversion  conversion_u1(
    36.                       .     sys_clk  (  sys_clk )  ,
    37.                       .     rst_n    (  rst_n   )  ,
    38.                       .     rx_done  (  rx_done )  ,
    39.                       .   trans_data (trans_data)  ,   0 1 2 3 4
    40.                       .     number   (  number  )
    41.  
    42.     );
    43.  
    44.   //解码器模块例化
    45.      wire  [3:0]      num   ;
    46.      wire  [7:0]      seg   ;
    47.   decoder  decoder_u1(
    48.                       .  num (num)  ,
    49.                       .  seg (seg)
    50.       );
    51.  
    52.   //数码管模块例化
    53.   SEG_state  SEG_state_u1(
    54.                         .    sys_clk ( sys_clk)  ,
    55.                         .    rst_n   ( rst_n  )  ,
    56.                         .   number   (number  ) ,//0~9999
    57.                         .   seg      (seg     ) ,
    58.                         .   DIG      (DIG     ) ,
    59.                         .   SEG      (SEG     ) ,
    60.                         .   num      (num     )
    61.  
    62.     );
    63.   
    64.  
    65.  
    66.  
    67.  
    68. endmodule

    接收端模块：

    1. `timescale 1ns / 1ps
    2. module uart_rx(
    3.      input                 sys_clk  ,
    4.      input                 rst_n    ,
    5.      input                 rx_data  ,
    6.      output    reg[7:0]    uart_data,
    7.      output    reg         rx_done
    8.  
    9.     );
    10.     parameter         SYSCLK =   50_000_000  ;
    11.     parameter         Baud   =   115200      ;
    12.     parameter         COUNT  =   SYSCLK/Baud ;//434   传输1比特所需要的时钟周期
    13.     parameter         MID    =   COUNT/2     ;
    14.     
    15.     reg       rx_reg1   ;
    16.     reg       rx_reg2   ;
    17.     
    18.     wire           start_flag ;
    19.     reg            rx_flag    ;
    20.     reg  [3:0]     cnt_bit    ;//0-9
    21.     reg  [9:0]     cnt        ;//0-434
    22.     reg  [7:0]     data_reg   ;
    23.     
    24.     always@(posedge sys_clk)
    25.           if(!rst_n)begin
    26.              rx_reg1 <= 1 ;
    27.              rx_reg2 <= 2 ;
    28.           end
    29.           else
    30.               begin
    31.                rx_reg1 <= rx_data  ;
    32.                rx_reg2 <= rx_reg1  ;
    33.               end
    34.      assign start_flag = ~rx_reg1 & rx_reg2 ;
    35.     
    36.     rx_flag
    37.     always@(posedge sys_clk)
    38.           if(!rst_n)
    39.              rx_flag <= 0 ;
    40.           else if (start_flag)
    41.              rx_flag <= 1 ;
    42.           else if ( cnt_bit == 9 && cnt == MID -1)
    43.              rx_flag <= 0 ;
    44.           else
    45.              rx_flag <= rx_flag ;
    46.     
    47.     /cnt  434
    48.      always@(posedge sys_clk)
    49.            if(!rst_n)
    50.               cnt <= 0 ;
    51.            else if ( rx_flag == 1)begin
    52.                 if ( cnt == COUNT -1 )
    53.                      cnt <= 0 ;
    54.                 else
    55.                      cnt <= cnt +1 ;
    56.                 end
    57.             else
    58.               cnt <= 0 ;
    59.     
    60.     
    61.     计数器
    62.     always@(posedge sys_clk)
    63.           if(!rst_n)
    64.              cnt_bit <= 0 ;
    65.           else if ( rx_flag)begin
    66.                if ( cnt == COUNT -1 )begin
    67.                     if( cnt_bit == 9 )
    68.                         cnt_bit <= 0 ;
    69.                     else
    70.                         cnt_bit <= cnt_bit +1;
    71.                     end
    72.                else
    73.                cnt_bit <= cnt_bit ;
    74.                end
    75.            else
    76.            cnt_bit <= 0 ; 
    77.    
    78.    /中间寄存器的赋值
    79.      always@(posedge sys_clk)
    80.            if(!rst_n)
    81.               data_reg <= 0 ;
    82.            else if ( rx_flag )begin
    83.                 if ( cnt == MID -1 && cnt_bit>0 && cnt_bit <9 )
    84.                  data_reg[cnt_bit -1] <= rx_data  ;
    85.                 else
    86.                  data_reg <= data_reg  ;
    87.            end
    88.            else
    89.            data_reg <= 0 ; 
    90.            
    91.   给uart_data赋值
    92.      always@(posedge sys_clk )
    93.            if(!rst_n)
    94.               uart_data <= 0 ;
    95.            else if ( rx_flag )begin
    96.                 if ( cnt_bit == 9 && cnt == MID/4 -1)
    97.                     uart_data <= data_reg  ;
    98.                 else
    99.                     uart_data <= uart_data  ;
    100.            end
    101.            else
    102.             uart_data <= uart_data  ;   
    103.             
    104.     rx_done
    105.       always@(posedge sys_clk )
    106.             if(!rst_n)
    107.                rx_done <= 0 ;
    108.             else if (rx_flag)begin
    109.                  if (cnt_bit == 9 && cnt == MID/2 -1)
    110.                      rx_done <= 1;
    111.                  else
    112.                      rx_done <= 0 ;            
    113.             end    
    114.             else
    115.               rx_done <= 0 ;
    116.     
    117. endmodule

    翻译模块：

    这里注释掉了组合逻辑的写法，因为根据仿真，组合逻辑引发了时序问题

    1. `timescale 1ns / 1ps
    2. module translate(
    3.       input              sys_clk   ,
    4.       input              rst_n     ,
    5.       input   [7:0]      uart_data ,
    6.       input              rx_done   ,
    7.       output  reg[7:0]   trans_data
    8.  
    9.     );
    10. //    always@(*)
    11. //          if(!rst_n)
    12. //             trans_data <= 0 ;
    13. //          else if (rx_done)
    14. //               case(uart_data)
    15. //               8'h30 : trans_data <= 8'd0  ; 
    16. //               8'h31 : trans_data <= 8'd1  ; 
    17. //               8'h32 : trans_data <= 8'd2  ; 
    18. //               8'h33 : trans_data <= 8'd3  ; 
    19. //               8'h34 : trans_data <= 8'd4  ; 
    20. //               default:;
    21. //               endcase
    22. //          else
    23. //             trans_data <= trans_data  ;
    24.  
    25.      always@(posedge sys_clk)
    26.           if(!rst_n)
    27.              trans_data <= 0 ;
    28.           else if (rx_done)
    29.                case(uart_data)
    30.                8'h30 : trans_data <= 8'd0  ; 
    31.                8'h31 : trans_data <= 8'd1  ; 
    32.                8'h32 : trans_data <= 8'd2  ; 
    33.                8'h33 : trans_data <= 8'd3  ; 
    34.                8'h34 : trans_data <= 8'd4  ; 
    35.                default:;
    36.                endcase
    37.           else
    38.              trans_data <= trans_data  ;
    39.    
    40. endmodule

    转换模块：

    1. `timescale 1ns / 1ps
    2. /*
    3. 发送4： 0111  显示4
    4. 发送3： 1011  显示3
    5. 发送2： 1101  显示2
    6. 发送1： 1110  显示1
    7. 发送0： 0000  显示0
    8. */
    9. module conversion(
    10.       input                sys_clk    ,
    11.       input                rst_n      ,
    12.       input                rx_done   ,
    13.       input  wire[7:0]   trans_data  ,   0 1 2 3 4
    14.       output wire[15:0]     number 
    15.  
    16.     );
    17.     /数据处理
    18.     reg[14:0]            trans_qian   ;     // 1000-9999
    19.     reg[10:0]            trans_bai    ;    //100-999 
    20.     reg[7:0]            trans_shi    ;   // 10-99
    21.     reg[4:0]            trans_ge     ;  //0-9
    22.     
    23.  
    24.     
    25.     
    26.     
    27.     ///状态机///
    28.     localparam               IDLE = 4'b0000 ;
    29.     localparam               GE   = 4'b0001 ;
    30.     localparam               SHI  = 4'b0010 ;
    31.     localparam               BAI  = 4'b0100 ;
    32.     localparam               QIAN = 4'b1000 ;
    33.  
    34.     
    35.     reg[4:0]        cur_state   ;
    36.     reg[4:0]        next_state  ;
    37.     //state1
    38.     always@(posedge sys_clk)
    39.           if(!rst_n)
    40.              cur_state <= IDLE  ;
    41.           else 
    42.              cur_state <= next_state  ;
    43.     
    44.     //state2
    45.     always@(*)
    46.           case(cur_state)
    47. //          IDLE : next_state = QIAN  ;
    48.           IDLE   :
    49.                   begin
    50.                       if (rx_done)
    51.                       next_state = QIAN  ;
    52.                       else
    53.                       next_state = cur_state ;
    54.                   end
    55.           QIAN   :
    56.                  begin
    57.                       if(rx_done)
    58.                          next_state = BAI  ;
    59.                       else
    60.                          next_state = cur_state  ;
    61.                  end
    62.           BAI  :
    63.                  begin
    64.                       if(rx_done)
    65.                          next_state = SHI  ;
    66.                       else
    67.                          next_state = cur_state  ;
    68.                  end
    69.           SHI  :
    70.                  begin
    71.                       if(rx_done)
    72.                          next_state = GE  ;
    73.                       else
    74.                          next_state = cur_state  ;
    75.                  end
    76.           GE :
    77.                  begin
    78.                       if(rx_done)
    79.                          next_state = IDLE  ;
    80.                       else
    81.                          next_state = cur_state  ;
    82.                  end
    83.           default:;
    84.           endcase
    85.           
    86.     state3
    87.     always@(posedge sys_clk)
    88.           if(!rst_n)
    89.                      begin
    90.                     trans_qian <= 0 ;
    91.                     trans_bai  <= 0 ;
    92.                     trans_shi  <= 0 ;
    93.                     trans_ge   <= 0 ;                   
    94.                     end
    95.           else
    96.              case(cur_state)
    97.              IDLE : 
    98.                     begin
    99.                     trans_qian <= 0 ;
    100.                     trans_bai  <= 0 ;
    101.                     trans_shi  <= 0 ;
    102.                     trans_ge   <= 0 ;                   
    103.                     end
    104.              QIAN : trans_qian <= trans_data * 1000 ;
    105.              BAI  : trans_bai  <= trans_data * 100  ;
    106.              SHI  : trans_shi  <= trans_data * 10   ;
    107.              GE   : trans_ge   <= trans_data * 1    ;
    108.              default:;
    109.              endcase
    110.     assign  number = trans_qian + trans_bai + trans_shi + trans_ge ;          
    111.  
    112. endmodule

    译码模块：

    1. `timescale 1ns / 1ps
    2. module decoder(
    3.     input      [3:0]   num   ,
    4.     output  reg[7:0]   seg
    5.     );
    6.     always@(*)
    7.     case(num)
    8.         4'd0: seg = 8'h3f;
    9.         4'd1: seg = 8'h06;
    10.         4'd2: seg = 8'h5b;
    11.         4'd3: seg = 8'h4f;
    12.         4'd4: seg = 8'h66;
    13.         4'd5: seg = 8'h6d;
    14.         4'd6: seg = 8'h7d;
    15.         4'd7: seg = 8'h07;
    16.         4'd8: seg = 8'h7f;
    17.         4'd9: seg = 8'h6f;
    18.         default:;
    19.      endcase
    20. endmodule

    数码管模块： 

    1. `timescale 1ns / 1ps
    2. module SEG_state(
    3.     input                sys_clk   ,
    4.     input                rst_n     ,
    5.     input  wire[15:0]   number    ,//0~9999
    6.     input  wire[7:0]    seg       ,
    7.     output wire[3:0]    DIG       ,
    8.     output wire[7:0]    SEG       ,
    9.     output reg[3:0]     num     
    10.  
    11.     );
    12.     parameter         MODE = 0 ;  ///共阴极
    13.     
    14.     ///数据处理
    15.     
    16. //    reg[3:0]         num     ;
    17. //    reg[7:0]         seg     ;
    18.     reg[3:0]         dig     ;
    19.     wire[3:0]      num_ge     ;
    20.     wire[3:0]      num_shi    ;
    21.     wire[3:0]      num_bai    ;
    22.     wire[3:0]      num_qian   ;
    23.     
    24.     assign          num_ge   = number%10        ;
    25.     assign          num_shi  = number/10%10     ;
    26.     assign          num_bai  = number/100%10    ;
    27.     assign          num_qian = number/1000%10   ;
    28.     
    29.     状态机
    30. //    parameter      TIME_1ms = 16'd50_000   ;   
    31.     parameter      TIME_1ms = 16'd5  ;    //测试用
    32.     
    33.     reg[3:0]        cur_state     ;
    34.     reg[3:0]        next_state    ;
    35.     reg[20:0]       cnt_1ms       ;
    36.     
    37.     localparam       IDLE = 4'b0000 ;
    38.     localparam       GE   = 4'b0001 ;
    39.     localparam       SHI  = 4'b0010 ;
    40.     localparam       BAI  = 4'b0100 ;
    41.     localparam       QIAN = 4'b1000 ;
    42.     
    43.     
    44.     always@(posedge sys_clk)
    45.           if(!rst_n)
    46.           cur_state <= IDLE  ;
    47.           else
    48.           cur_state <= next_state  ;
    49.           
    50.     always@(*)
    51.           case(cur_state)
    52.           IDLE :next_state = GE ;
    53.           GE   :
    54.                 begin
    55.                     if( cnt_1ms == TIME_1ms -1 )
    56.                        next_state = SHI  ;
    57.                     else
    58.                        next_state = cur_state ;
    59.                 end
    60.           SHI  :
    61.                 begin
    62.                     if( cnt_1ms == TIME_1ms -1 )
    63.                        next_state = BAI  ;
    64.                     else
    65.                        next_state = cur_state ;
    66.                 end
    67.           BAI  :
    68.                 begin
    69.                     if( cnt_1ms == TIME_1ms -1 )
    70.                        next_state = QIAN  ;
    71.                     else
    72.                        next_state = cur_state ;
    73.                 end
    74.           QIAN :
    75.                 begin
    76.                     if( cnt_1ms == TIME_1ms -1 )
    77.                        next_state = GE  ;
    78.                     else
    79.                        next_state = cur_state ;
    80.                 end
    81.             default:;
    82.           endcase
    83.    
    84.    always@(posedge sys_clk )
    85.          if(!rst_n)begin
    86.             dig <= 0     ;
    87.             cnt_1ms <= 0 ;
    88.             num <= 0     ;
    89.          end
    90.          else
    91.          case(cur_state)
    92.          IDLE : 
    93.                begin
    94.                     dig <= 0 ; 
    95.                     cnt_1ms <= 0 ;
    96.                     num <= 0;
    97.                end
    98.          GE   : 
    99.                begin
    100.                dig <= 4'b1110  ;              
    101.                num <= num_ge   ;
    102.                if( cnt_1ms == TIME_1ms -1 )
    103.                    cnt_1ms <= 0 ;
    104.                else
    105.                    cnt_1ms <= cnt_1ms +1 ;
    106.                end
    107.          SHI  :
    108.                begin
    109.                dig <= 4'b1101  ;              
    110.                num <= num_shi   ;
    111.                if( cnt_1ms == TIME_1ms -1 )
    112.                    cnt_1ms <= 0 ;
    113.                else
    114.                    cnt_1ms <= cnt_1ms +1 ;
    115.                end 
    116.          BAI  :
    117.                begin
    118.                dig <= 4'b1011  ;              
    119.                num <= num_bai   ;
    120.                if( cnt_1ms == TIME_1ms -1 )
    121.                    cnt_1ms <= 0 ;
    122.                else
    123.                    cnt_1ms <= cnt_1ms +1 ;
    124.                end 
    125.          QIAN : 
    126.                begin
    127.                dig <= 4'b0111  ;              
    128.                num <= num_qian   ;
    129.                if( cnt_1ms == TIME_1ms -1 )
    130.                    cnt_1ms <= 0 ;
    131.                else
    132.                    cnt_1ms <= cnt_1ms +1 ;
    133.                end
    134.          default:;
    135.          endcase
    136.     
    137.     assign         DIG = (MODE == 0 ) ? dig : ~dig ;
    138.     assign         SEG = (MODE == 0 ) ? seg : ~seg ;
    139.                
    140. endmodule

    四、仿真文件

    1. `timescale 1ns / 1ps
    2. module test_bench(  );
    3.  
    4.     reg                sys_clk   ;
    5.     reg                rst_n     ;
    6.     reg                rx_data   ;
    7.     wire[3:0]           DIG      ;
    8.     wire[7:0]           SEG      ;
    9.     
    10.     parameter         SYSCLK = 50_000_000  ;  
    11.     parameter         Baud   = 115200      ;
    12.     parameter         COUNT  = SYSCLK/Baud ;
    13.     parameter         MID    = COUNT/2     ;
    14.     
    15.     initial
    16.            begin
    17.                  sys_clk  = 0 ;
    18.                  rst_n    = 0 ;
    19.                  #10
    20.                  rst_n    = 1 ;
    21.            end
    22.     always #1 sys_clk = ~sys_clk  ;
    23.     
    24.     initial
    25.            begin
    26.                 uart_out (8'h31)  ;
    27.                 uart_out (8'h32)  ;
    28.                 uart_out (8'h33)  ;
    29.                 uart_out (8'h34)  ;
    30.             end
    31.             
    32.     任务函数
    33.     task              uart_out  ;
    34.     input    [7:0]     DATA     ;
    35.          begin
    36.               rx_data = 1   ;空闲位初始
    37.               #20
    38.               rx_data = 0   ;起始位
    39.         
    40.                #(COUNT*2)  rx_data = DATA[0] ;///数据位第一位
    41.                #(COUNT*2)  rx_data = DATA[1] ;///数据位第二位
    42.                #(COUNT*2)  rx_data = DATA[2] ;
    43.                #(COUNT*2)  rx_data = DATA[3] ;
    44.                #(COUNT*2)  rx_data = DATA[4] ;
    45.                #(COUNT*2)  rx_data = DATA[5] ;
    46.                #(COUNT*2)  rx_data = DATA[6] ;
    47.                #(COUNT*2)  rx_data = DATA[7] ;
    48.                #(COUNT*2)  rx_data = 1       ;
    49.                #(COUNT*2)                    ;//停止位也需要时间
    50.                #200;//0_000                     ;
    51.            end                  //2ms数据发送的时间至少要大于点阵屏切换数据的时间（1ms）
    52.     endtask
    53.  
    54. TOP TOP_u1(
    55.              .     sys_clk  (sys_clk)  ,
    56.              .     rst_n    (rst_n  )  ,
    57.              .     rx_data  (rx_data)  ,
    58.              .     DIG      (DIG    )  ,
    59.              .     SEG      (SEG    ) 
    60.     );
    61. endmodule

    仿真结果：

    五、绑定管脚

    1.  
    2. set_property PACKAGE_PIN P20 [get_ports {DIG[0]}]
    3. set_property PACKAGE_PIN N18 [get_ports {DIG[1]}]
    4. set_property PACKAGE_PIN P18 [get_ports {DIG[2]}]
    5. set_property PACKAGE_PIN W16 [get_ports {DIG[3]}]
    6. set_property IOSTANDARD LVCMOS33 [get_ports {DIG[3]}]
    7. set_property IOSTANDARD LVCMOS33 [get_ports {DIG[2]}]
    8. set_property IOSTANDARD LVCMOS33 [get_ports {DIG[1]}]
    9. set_property IOSTANDARD LVCMOS33 [get_ports {DIG[0]}]
    10. set_property PACKAGE_PIN R18 [get_ports {SEG[0]}]
    11. set_property PACKAGE_PIN N20 [get_ports {SEG[1]}]
    12. set_property PACKAGE_PIN U20 [get_ports {SEG[2]}]
    13. set_property PACKAGE_PIN W20 [get_ports {SEG[3]}]
    14. set_property PACKAGE_PIN R17 [get_ports {SEG[4]}]
    15. set_property PACKAGE_PIN P19 [get_ports {SEG[5]}]
    16. set_property PACKAGE_PIN T20 [get_ports {SEG[6]}]
    17. set_property PACKAGE_PIN V20 [get_ports {SEG[7]}]
    18. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[7]}]
    19. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[6]}]
    20. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[5]}]
    21. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[4]}]
    22. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[3]}]
    23. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[2]}]
    24. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[1]}]
    25. set_property IOSTANDARD LVCMOS33 [get_ports {SEG[0]}]
    26.  
    27. set_property PACKAGE_PIN P15 [get_ports rst_n]
    28. set_property PACKAGE_PIN K17 [get_ports sys_clk]
    29. set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
    30. set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
    31.  
    32. set_property IOSTANDARD LVCMOS33 [get_ports rx_data]
    33. set_property PACKAGE_PIN W18 [get_ports rx_data]

    六、实验结果

    0623

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  • 原文地址：https://blog.csdn.net/loveyousosad/article/details/139900627