[HDLBits] Exams/ece241 2014 q5a

You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
	//分三种状态，用当前输出为几+是否产生进位来记录状态，0有、1无、0无三种，因为不会有某位为1还进过位的。
    parameter you0=0,wu1=1,wu0=2;
    reg [1:0]state,next;
    always@(*) begin
        case(state)
            you0:next<=x?wu1:you0;
            wu1:next<=x?wu0:wu1;
            wu0:next<=x?wu0:wu1;
        endcase
    end
    always@(posedge clk or posedge areset) begin
        if(areset)
            state<=you0;
        else
            state<=next;
    end
    assign z=(state==wu1)?1:0;
endmodule
//好好好，给我聪明完了。确实要先做下一题再回来做这个，简单不少

最好先做下一题再做这个