HDL-Bits 刷题记录 04

More Circuits

Rule90

元胞自动机，网上给的元胞自动机的解释是按照一定规律生成/扩散的数据格式

上面那个表意义不大，就能看出来是左右异或得到中间数主要看下面的
1
10
101
1000
10100
100010
1010101
10000000
下面简答迭代一下

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    always @(posedge clk)
        begin
            if(load)
                q <= data;
            else
                q <= {1'b0,q[511:1]}^{q[510:0],1'b0};//错位异或的写法
        end
endmodule

Rule110

这个关系反正我是没看出来，
按照网上一个哥们的解法，卡诺图化简

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    always @(posedge clk)
        begin
            if(load)
                q <= data;
            else
                q <= (q & ~{q[510:0],1'b0}) | (~{1'b0,q[511:1]} & {q[510:0],1'b0}) | (~q & {q[510:0],1'b0}); 
        end
endmodule

Finite State Machu

Fsm1

状态机图解释，输入为1的时候状态保持，输入为0 状态反转，复位时候状态复位为B
状态A 输出0 状态B 输出1
不知道带next_state 怎么写 就给干掉了 果然简单多了 不知道是不是练习的重点

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        case (state)
        A: out = 0;
        B: out = 1;
        endcase
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        if(areset) begin
 //           next_state <= 1'b1;
            state <= 1'b1;
        end
        else if(in==1'b1) begin
//            next_state <= state;
            state <= state;
        end
        else begin
//            next_state <= ~next_state;
            state <= ~state;
        end
    end

    // Output logic
    // assign out = (state == ...);
endmodule

Fsm1s

和上一题一样 要同步复位
我还是不会他的思路怎么填充 西八

module top_module(
    input clk,
    input reset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) begin    // This is a combinational always block
        // State transition logic
        case (state)
        A: out = 0;
        B: out = 1;
        endcase
    end

    always @(posedge clk) begin    // This is a sequential always block
        if(reset) begin
 //           next_state <= 1'b1;
            state <= 1'b1;
        end
        else if(in==1'b1) begin
//            next_state <= state;
            state <= state;
        end
        else begin
//            next_state <= ~next_state;
            state <= ~state;
        end
    end

    // Output logic
    // assign out = (state == ...);

endmodule

Fsm2

虽然我可能还是猜不出来他想怎么写 但是我能让我的代码好看点,至少把他定义的变量都用上了，虽然没有什么卵用

module top_module(
    input clk,
    input areset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=0, ON=1; 
    reg state, next_state;
    always @(*) begin
        state = next_state;
    end
    always @(posedge clk, posedge areset) begin
        if(areset)begin
        
        next_state <=1'b0;
        end
        else begin
        case (state)
        OFF: next_state <= j?ON:OFF;
        ON:  next_state <= k?OFF:ON;
        endcase
        end
    end
    // Output logic
     assign out = state ? 1:0;

endmodule

Fsm2s

应该是异步逻辑改成同步

module top_module(
    input clk,
    input reset,    // Asynchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF=1'b0, ON=1'b1; 
    reg state, next_state;
    always @(*) begin
        state = next_state;
    end
    always @(posedge clk) begin
        if(reset)begin
        
        next_state <=1'b0;
        end
        else begin
        case (state)
        OFF: next_state <= j?ON:OFF;
        ON:  next_state <= k?OFF:ON;
        endcase
        end
    end
    // Output logic
     assign out = state ? 1'b1:1'b0;

endmodule

Fsm3comb

A=2’b00, B=2’b01, C=2’b10, D=2’b11.
根据输入给输出赋值 纯组合逻辑 分两行写是因为开始没看到没有时钟

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;
    always @ (*) begin
        
        out = (D==state)?1:0; 

    end
    always @(*) begin
        case (state) 
        A: next_state= in?B:A;
        B: next_state= in?B:C;
        C: next_state= in?D:A;
        D: next_state= in?B:C;
        endcase
    end
    // State transition logic: next_state = f(state, in)

    // Output logic:  out = f(state) for a Moore state machine

endmodule

Fsm3onehot

就是单纯的分解成每个bit位和输入状态的对应关系
做状态转换和输出逻辑

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = ~in&&(state[A]||state[C]);
    assign next_state[B] = in&&(state[A]||state[B]||state[D]);
    assign next_state[C] = ~in&&(state[B]||state[D]);
    assign next_state[D] = in&&(state[C]);

    // Output logic: 
    assign out = (state&8)?1:0;

endmodule

Fsm3

这几个的逻辑基本都没变化

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
    parameter A =3'd1,B = 3'd3,C = 3'd2,D = 3'd6;
    reg [3:0] state,next_state;
    always@(posedge clk or posedge areset) begin
        if(areset) begin
            next_state <= A;
        end
        else begin
            case (state)
            A:next_state<= in? B:A;
            B:next_state<= in? B:C;
            C:next_state<= in? D:A;
            D:next_state<= in? B:C;
            endcase 
        end
    end
    assign state = next_state;
    assign out =state ==D?1:0;
endmodule

官方答案如下：

module top_module (
	input clk,
	input in,
	input areset,
	output out
);
	// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
	// It doesn't really matter what assignment is used, as long as they're unique.
	parameter A=0, B=1, C=2, D=3;
	reg [1:0] state;		// Make sure state and next are big enough to hold the state encodings.
	reg [1:0] next;

    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.    
    always@(*) begin
		case (state)
			A: next = in ? B : A;
			B: next = in ? B : C;
			C: next = in ? D : A;
			D: next = in ? B : C;
		endcase
    end
    // Edge-triggered always block (DFFs) for state flip-flops. Asynchronous reset.
    always @(posedge clk, posedge areset) begin
		if (areset) state <= A;
        else state <= next;
	end
	// Combinational output logic. In this problem, an assign statement is the simplest.		
	assign out = (state==D);
endmodule

Fsm3s

问题同上，异步复位改同步复位

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    parameter A =3'd1,B = 3'd3,C = 3'd2,D = 3'd6;
    reg [3:0] state,next_state;
    always@(posedge clk ) begin
        if(reset) begin
            next_state <= A;
        end
        else begin
            case (state)
            A:next_state<= in? B:A;
            B:next_state<= in? B:C;
            C:next_state<= in? D:A;
            D:next_state<= in? B:C;
            endcase 
        end
    end
    assign state = next_state;
    assign out =state ==D?1:0;
endmodule

ece241 2013 q4

分析一下题，这两天脑子嗡嗡的，不好使
同步复位
状态在S1之下的时候 (=0) F1 F2 F3 全输出
前三个都属于正常范畴 恶心的是dfr
关于他的描述是 当水位变化前比变化后 高的时候 dfr = 1 ,否则(水位不变化)dfr维持不变
没想到在哪用状态机 就没用

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    reg [3:1] s1;

    always@(posedge clk) begin
        if(reset) begin
            fr3<=1'b1;
            fr2<=1'b1;
            fr1<=1'b1;
        end
        else begin
            case (s[3:1]) 
            3'b000: {fr3,fr2,fr1} <= 3'b111;
            3'b001: {fr3,fr2,fr1} <= 3'b011;
            3'b011: {fr3,fr2,fr1} <= 3'b001;
            3'b111: {fr3,fr2,fr1} <= 3'b000;
            default:  {fr3,fr2,fr1} <= 3'b111;
            endcase
        end
    end
    always@(posedge clk) begin 
        if(reset)
            s1[3:1]<=3'b000;
        else 
            s1[3:1]<=s[3:1];
    end    
    always@(posedge clk) begin 
        if(reset)
            dfr<=1'b1;
        else if (s1 == s)
            dfr<=dfr;
        else 
            dfr<= ((s1>=s))?1:0;
    end    
endmodule

官方答案如下：
着实看不进去了，改天解释一下

module top_module (
	input clk,
	input reset,
	input [3:1] s,
	output reg fr3,
	output reg fr2,
	output reg fr1,
	output reg dfr
);


	// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
	// It doesn't really matter what assignment is used, as long as they're unique.
	// We have 6 states here.
	parameter A2=0, B1=1, B2=2, C1=3, C2=4, D1=5;
	reg [2:0] state, next;		// Make sure these are big enough to hold the state encodings.
	


    // Edge-triggered always block (DFFs) for state flip-flops. Synchronous reset.	
	always @(posedge clk) begin
		if (reset) state <= A2;
		else state <= next;
	end

    // Combinational always block for state transition logic. Given the current state and inputs,
    // what should be next state be?
    // Combinational always block: Use blocking assignments.    
	always@(*) begin
		case (state)
			A2: next = s[1] ? B1 : A2;
			B1: next = s[2] ? C1 : (s[1] ? B1 : A2);
			B2: next = s[2] ? C1 : (s[1] ? B2 : A2);
			C1: next = s[3] ? D1 : (s[2] ? C1 : B2);
			C2: next = s[3] ? D1 : (s[2] ? C2 : B2);
			D1: next = s[3] ? D1 : C2;
			default: next = 'x;
		endcase
	end
	
	// Combinational output logic. In this problem, a procedural block (combinational always block) 
	// is more convenient. Be careful not to create a latch.
	always@(*) begin
		case (state)
			A2: {fr3, fr2, fr1, dfr} = 4'b1111;
			B1: {fr3, fr2, fr1, dfr} = 4'b0110;
			B2: {fr3, fr2, fr1, dfr} = 4'b0111;
			C1: {fr3, fr2, fr1, dfr} = 4'b0010;
			C2: {fr3, fr2, fr1, dfr} = 4'b0011;
			D1: {fr3, fr2, fr1, dfr} = 4'b0000;
			default: {fr3, fr2, fr1, dfr} = 'x;
		endcase
	end
endmodule