• 基于FPGA的OV7670摄像头实时检测

    目录

    前言：整体系统框图

    一、OV7670摄像头简介

    二、OV7670 SCCB协议简介

    三、OV7670初始化寄存器配置

    四、OV7670初始化代码编写

     五、什么是DVP?

    六、摄像头写数据请求

    七、顶层文件编写

    八、效果

    前言：整体系统框图

     如图所示，FPGA中主要模块包含：时钟模块、OV7670初始化模块、DVP协议数据流模块、写FIFO模块、写FIFO控制模块、SDRAM控制模块、读FIFO模块、读FIFO控制模块、VGA控制模块。

    其整体流程为：启动时先对摄像头进行初始化设置，初始化完成后，FPGA从摄像头获取一帧一帧的图像数据，根据数据手册将ov7670数据流转换成我们需要的RGB565数据流，随后存入写FIFO模块；（写控制模块）当写FIFO模块中存储的数据大于等于8时，发出SDRAM写请求，SDRAM写请求通过后，读取FIFO数据存储起来；（读FIFO模块）当读FIFO数据小于等于8时，读取SDRAM中的数据经过读FIFO缓存后送入VGA显示模块进行显示。同时写控制模块和读控制模块控制SDRAM读写地址的增加。

    1、时钟模块
         这里使用PLL的IP核，以50MHz时钟生成25MHz和100MHz时钟，其中摄像头初始化模块和VGA控制模块使用的是25MHz，SDRAM控制模块、写FIFO控制模块和读FIFO控制模块使用的是100MHz，写FIFO和读FIFO模块都是异步FIFO，使用25MHz和100MHz时钟。

    一、OV7670摄像头简介

    OV7670/OV7171 图像传感器，体积小、工作电压低，提供单片VGA摄像头和影像处理器的所有功能。通过SCCB 总线控制，可以输出整帧、子采样、取窗口等方式的各种分辨率8位影响数据。该产品VGA图像最高达到30帧/秒。用户可以完全控制图像质量、数据格式和传输方式。所有图像处理功能过程包括伽玛曲线、白平衡、饱和度、色度等都可以通过SCCB接口编程。OmmiVision 图像传感器应用独有的传感器技术，通过减少或消除光学或电子缺陷如固定图案噪声、托尾、浮散等，提高图像质量，得到清晰的稳定的彩色图像。

    主要引出的信号引脚如下：

    3.3V--输入电源电压(推荐使用3.3V,5V也可，但不推荐)

    GND

    SCL(SIOC)：SCCB时钟口(注意：部分单片机需要上拉控制，和I2C接口类似)

    SDA(SIOD)：SCCB数据口(注意：部分单片机需要上拉控制，和I2C接口类似)

    VSYNC：场同步（帧同步）信号(输出信号)

    HREF：行同步信号(输出信号，一般可以不使用，特殊情况使用)

    PCLK：像素时钟

    XCLK：系统时钟输入

    D0-D7:数据位(输出信号)

    RESET：初始化所有寄存器到默认值 0：RESET 模式 1：一般模式

    PWDN：POWER DOWN模式选择 0：工作 1：POWER DOWN

    其中，对OV7670初始化配置只使用SCL和SDA两个信号线。

    所用模块如图：

    二、OV7670 SCCB协议简介

          对OV7670初始化使用的是SCCB协议，由数据线SDA和时钟线SCL组成，SCCB协议和I2C协议基本一样，是简化的I2C协议，前面博客中已经讲过I2C协议，需要可以去看看。

    SCCB(SeriaI Camera ControlBus)是简化的I2C协议，SIO-l是串行时钟输入线，SIO-O是串行双向数据线，分别相当于I2C协议的SCL和SDA。SCCB的总线时序与I2C基本相同，它的响应信号ACK被称为一个传输单元的第9位，分为Don’t care和NA。Don’t care位由从机产生;NA位由主机产生，由于SCCB不支持多字节的读写，NA位必须为高电平。另外，SCCB没有重复起始的概念，因此在SCCB的读周期中，当主机发送完片内寄存器地址后，必须发送总线停止条件。不然在发送读命令时，从机将不能产生Don’t care响应信号。

    这里采用的是100KHz的SCL。

    三、OV7670初始化寄存器配置

         OV7670摄像头共201个寄存器，需要配置的有一百六十几个，这个具体看数据手册吧，下边代码中会有配置寄存器的数据。

    四、OV7670初始化代码编写

    1. `timescale 1 ns / 1 ns
    2. module system_ctrl
    3. (
    4. 	input 		clk,		//50MHz
    5. 	input 		rst_n,		//global reset
    6.  
    7. 	output 		sys_rst_n,	//system reset
    8. 	output 		clk_c0,		
    9. 	output 		clk_c1,
    10. 	output		clk_c2,	//-75deg
    11. 	output		clk_c3	//-75deg
    12. );
    13.  
    14. //----------------------------------------------
    15. //rst_n synchronism, is controlled by the input clk
    16. reg     rst_nr1,rst_nr2;
    17. always @(posedge clk or negedge rst_n)
    18. begin
    19. 	if(!rst_n)
    20. 		begin
    21. 		rst_nr1 <= 1'b0;
    22. 		rst_nr2 <= 1'b0;
    23. 		end
    24. 	else
    25. 		begin
    26. 		rst_nr1 <= 1'b1;
    27. 		rst_nr2 <= rst_nr1;
    28. 		end
    29. end
    31. //----------------------------------
    32. //component instantiation for system_delay
    33. wire	delay_done;
    34. system_delay	u_system_delay
    35. (
    36. 	.clk		(clk),
    37. 	.rst_n		(rst_nr2),
    38. 	.delay_done	(delay_done)
    39. );
    40. wire	pll_rst = ~rst_nr2 & ~delay_done;	//active High
    42. //----------------------------------------------
    43. //Component instantiation
    44. wire 	locked;	
    45. sdram_pll	u_sdram_pll
    46. (
    47. 	.inclk0	(clk),
    48. 	.areset	(pll_rst),
    49. 	.locked	(locked),
    50. 			
    51. 	.c0		(clk_c0),
    52. 	.c1		(clk_c1),
    53. 	.c2		(clk_c2),
    54. 	.c3		(clk_c3)
    55. );
    59. //----------------------------------------------
    60. //sys_rst_n synchronism, is control by the highest output clk
    61.   
    62. wire	sysrst_nr0 = rst_nr2 & locked & delay_done;  
    63. reg 	sysrst_nr1, sysrst_nr2; 
    64. always @(posedge clk_c1 or negedge sysrst_nr0)
    65. begin
    66. 	if(!sysrst_nr0) 
    67.         begin
    68.         sysrst_nr1 <= 1'b0;
    69.         sysrst_nr2 <= 1'b0;
    70.         end        
    71. 	else 
    72.         begin
    73.         sysrst_nr1 <= 1'b1;
    74.         sysrst_nr2 <= sysrst_nr1;
    75.         end
    76. end
    77. assign sys_rst_n = sysrst_nr2;	//active Low
    78.  
    79. endmodule
    80.  
    81. //################################################//
    82. //################################################//
    83.  
    84. module system_delay
    85. (
    86. 	input	clk,		//50MHz
    87. 	input	rst_n,
    88. 	output	delay_done
    89. );
    90.  
    91. //------------------------------------------
    92. // Delay 100ms for steady state
    93. localparam	DELAY_CNT = 23'd100_0000;	//50ms
    94. reg	[22:0] cnt;
    95. always@(posedge clk or negedge rst_n)
    96. begin
    97. 	if(!rst_n)
    98. 		cnt <= 0;
    99. 	else
    100. 		begin
    101. 		if(cnt < DELAY_CNT) //1ms
    102. 			cnt <= cnt + 1'b1;
    103. 		else
    104. 			cnt <= cnt;
    105. 		end
    106. end
    107.  
    108. //------------------------------------------
    109. //sys_rst_n synchronism
    110. assign	delay_done = (cnt == DELAY_CNT)? 1'b1 : 1'b0;
    111.  
    112. endmodule

    摄像头检测代码

    1. `timescale 1ns/1ns
    2. module CMOS_Capture
    3. (
    4. 	//Global Clock
    5. 	input				iCLK,			//25MHz
    6. 	input				iRST_N,
    7.  
    8. 	//I2C Initilize Done
    9. 	input				Init_Done,		//Init Done
    10. 	
    11. 	//Sensor Interface
    12. 	output				CMOS_RST_N,		//cmos work state(5ms delay for sccb config)
    13. 	output				CMOS_PWDN,      //cmos power on	
    14. 	output				CMOS_XCLK,		//25MHz
    15. 	input				CMOS_PCLK,		//25MHz
    16. 	input	[7:0]		CMOS_iDATA,		//CMOS Data
    17. 	input				CMOS_VSYNC,		//L: Vaild
    18. 	input				CMOS_HREF,		//H: Vaild
    19. 	
    20. 	//Ouput Sensor Data
    21. 	output	reg			CMOS_oCLK,		//1/2 PCLK
    22. 	output	reg	[15:0]	CMOS_oDATA,		//16Bits RGB		
    23. 	output	reg			CMOS_VALID,		//Data Enable
    24. 	output	reg	[7:0]	CMOS_FPS_DATA	//cmos fps
    25. );
    26. assign	CMOS_RST_N = 1'b1;		//cmos work state(5ms delay for sccb config)
    27. assign  CMOS_PWDN = 1'b0;		//cmos power on	
    28. assign	CMOS_XCLK = iCLK;		//25MHz XCLK
    29.  
    30.  
    31. //-----------------------------------------------------
    32. //同步输入//Sensor HS & VS Vaild Capture
    33. /**************************************************
    34. ________							       ________
    35. VS		|_________________________________|
    36. HS			  _______	 	   _______
    37. _____________|       |__...___|       |____________
    38. **************************************************/
    39.  
    40. /*
    41. //----------------------------------------------
    42. reg		mCMOS_HREF;		//行同步：高电平有效
    43. always@(posedge CMOS_PCLK or negedge iRST_N)
    44. begin
    45. 	if(!iRST_N)
    46. 		mCMOS_HREF <= 0;
    47. 	else
    48. 		mCMOS_HREF <= CMOS_HREF;		
    49. end
    50. wire	CMOS_HREF_over = ({mCMOS_HREF,CMOS_HREF} == 2'b10) ? 1'b1 : 1'b0;		//HREF 下降沿结束
    51. */
    53. //----------------------------------------------
    54. reg		mCMOS_VSYNC;
    55. always@(posedge CMOS_PCLK or negedge iRST_N)
    56. begin
    57. 	if(!iRST_N)
    58. 		mCMOS_VSYNC <= 1;
    59. 	else
    60. 		mCMOS_VSYNC <= CMOS_VSYNC;		//场同步：低电平有效
    61. end
    62. wire	CMOS_VSYNC_over = ({mCMOS_VSYNC,CMOS_VSYNC} == 2'b01) ? 1'b1 : 1'b0;	//VSYNC上升沿结束
    63.  
    64.  
    65. /*
    66. //--------------------------------------------
    67. //Counter the HS & VS Pixel
    68. localparam		H_DISP	=	12'd640;
    69. localparam		V_DISP	=	12'd480;
    70. reg		[11:0]	X_Cont;	//640
    71. reg		[11:0]	Y_Cont;	//480
    72. always@(posedge CMOS_PCLK or negedge iRST_N)
    73. begin
    74. 	if(!iRST_N)
    75. 		X_Cont <= 0;
    76. 	else if(~CMOS_VSYNC & CMOS_HREF)			//场信号有效
    77. 		X_Cont <= (byte_state == 1'b1) ?  X_Cont + 1'b1 : X_Cont;
    78. 	else
    79. 		X_Cont <= 0;
    80. end
    81.  
    82. always@(posedge CMOS_PCLK or negedge iRST_N)
    83. begin
    84. 	if(!iRST_N)
    85. 		Y_Cont <= 0;
    86. 	else if(CMOS_VSYNC == 1'b0)
    87. 		begin
    88. 		if(CMOS_HREF_over == 1'b1)		//HREF下降沿 一行结束
    89. 			Y_Cont <= Y_Cont + 1'b1;
    90. 		end
    91. 	else
    92. 		Y_Cont <= 0;
    93. end
    94. */
    96. //-----------------------------------------------------
    97. //Change the sensor data from 8 bits to 16 bits.
    98. reg			byte_state;		//byte state count
    99. reg [7:0]  	Pre_CMOS_iDATA;
    100. always@(posedge CMOS_PCLK or negedge iRST_N)
    101. begin
    102. 	if(!iRST_N)
    103. 		begin
    104. 		byte_state <= 0;
    105. 		Pre_CMOS_iDATA <= 8'd0;
    106. 		CMOS_oDATA <= 16'd0;
    107. 		end
    108. 	else
    109. 		begin
    110. 		if(~CMOS_VSYNC & CMOS_HREF)			//行场有效，{first_byte, second_byte} 
    111. 			begin
    112. 			byte_state <= byte_state + 1'b1;	//（RGB565 = {first_byte, second_byte}）
    113. 			case(byte_state)
    114. 			1'b0 :	Pre_CMOS_iDATA[7:0] <= CMOS_iDATA;
    115. 			1'b1 : 	CMOS_oDATA[15:0] <= {Pre_CMOS_iDATA[7:0], CMOS_iDATA[7:0]};
    116. 			endcase
    117. 			end
    118. 		else
    119. 			begin
    120. 			byte_state <= 0;
    121. 			Pre_CMOS_iDATA <= 8'd0;
    122. 			CMOS_oDATA <= CMOS_oDATA;
    123. 			end
    124. 		end
    125. end
    128. //--------------------------------------------
    129. //Wait for Sensor output Data valid， 10 Franme
    130. reg	[3:0] 	Frame_Cont;
    131. reg 		Frame_valid;
    132. always@(posedge CMOS_PCLK or negedge iRST_N)
    133. begin
    134. 	if(!iRST_N)
    135. 		begin
    136. 		Frame_Cont <= 0;
    137. 		Frame_valid <= 0;
    138. 		end
    139. 	else if(Init_Done)					//CMOS I2C初始化完毕
    140. 		begin
    141. 		if(CMOS_VSYNC_over == 1'b1)		//VS上升沿，1帧写入完毕
    142. 			begin
    143. 			if(Frame_Cont < 12)
    144. 				begin
    145. 				Frame_Cont	<=	Frame_Cont + 1'b1;
    146. 				Frame_valid <= 1'b0;
    147. 				end
    148. 			else
    149. 				begin
    150. 				Frame_Cont	<=	Frame_Cont;
    151. 				Frame_valid <= 1'b1;		//数据输出有效
    152. 				end
    153. 			end
    154. 		end
    155. end
    157. //-----------------------------------------------------
    158. //CMOS_DATA数据同步输出使能时钟
    159. always@(posedge CMOS_PCLK or negedge iRST_N)
    160. begin
    161. 	if(!iRST_N)
    162. 		CMOS_oCLK <= 0;
    163. 	else if(Frame_valid == 1'b1 && byte_state)//(X_Cont >= 12'd1 && X_Cont <= H_DISP))
    164. 		CMOS_oCLK <= ~CMOS_oCLK;
    165. 	else
    166. 		CMOS_oCLK <= 0;
    167. end
    169. //----------------------------------------------------
    170. //数据输出有效CMOS_VALID
    171. always@(posedge CMOS_PCLK or negedge iRST_N)
    172. begin
    173. 	if(!iRST_N)
    174. 		CMOS_VALID <= 0;
    175. 	else if(Frame_valid == 1'b1)
    176. 		CMOS_VALID <= ~CMOS_VSYNC;
    177. 	else
    178. 		CMOS_VALID <= 0;
    179. end
    180.  
    181.  
    182. /************************************************************
    183. 	Caculate Frame Rate per second
    184. *************************************************************/
    185. //-----------------------------------------------------
    186. //	2s 延时函数
    187. reg	[25:0]	delay_cnt;	//25_000000 * 2
    188. always@(posedge iCLK or negedge iRST_N)
    189. begin
    190. 	if(!iRST_N)
    191. 		delay_cnt <= 0;
    192. 	else if(Frame_valid)
    193. 		begin
    194. 		if(delay_cnt < 26'd50_000000)
    195. 			delay_cnt <= delay_cnt + 1'b1;
    196. 		else
    197. 			delay_cnt <= 0;
    198. 		end
    199. 	else
    200. 		delay_cnt <= 0;
    201. end
    202. wire	delay_2s = (delay_cnt == 26'd50_000000) ? 1'b1 : 1'b0;
    204. //-------------------------------------------
    205. //帧率采样计算
    206. reg			fps_state;
    207. reg	[7:0]	fps_data;
    208. always@(posedge iCLK or negedge iRST_N)
    209. begin
    210. 	if(!iRST_N)
    211. 		begin
    212. 		fps_data <= 0;
    213. 		fps_state <= 0;
    214. 		CMOS_FPS_DATA <= 0;
    215. 		end
    216. 	else if(Frame_valid)
    217. 		begin
    218. 		case(fps_state)
    219. 		0:	begin
    220. 			CMOS_FPS_DATA <= CMOS_FPS_DATA;
    221. 			if(delay_2s == 0)
    222. 				begin
    223. 				fps_state <= 0;
    224. 				if(CMOS_VSYNC_over == 1'b1)		//VS上升沿，1帧写入完毕
    225. 					fps_data <= fps_data + 1'b1;
    226. 				end
    227. 			else
    228. 				fps_state <= 1;
    229. 			end
    230. 		1:	begin
    231. 			fps_state <= 0;
    232. 			fps_data <= 0;
    233. 			CMOS_FPS_DATA <= fps_data >>1;
    234. 			end
    235. 		endcase
    236. 		end
    237. 	else
    238. 		begin
    239. 		fps_data <= 0;
    240. 		fps_state <= 0;
    241. 		CMOS_FPS_DATA <= 0;
    242. 		end
    243. end
    246. endmodule

    摄像头开机定时要求

    1. //camera power on timing requirement
    2. module power_on_delay(clk_50M,reset_n,camera_rstn,camera_pwnd,initial_en);                  
    3. input clk_50M;
    4. input reset_n;
    5. output camera_rstn;
    6. output camera_pwnd;
    7. output initial_en;
    8. reg [18:0]cnt1;
    9. reg [15:0]cnt2;
    10. reg [19:0]cnt3;
    11. reg initial_en;
    12. reg camera_rstn_reg;
    13. reg camera_pwnd_reg;
    14.  
    15. assign camera_rstn=camera_rstn_reg;
    16. assign camera_pwnd=camera_pwnd_reg;
    17.  
    18. //5ms, delay from sensor power up stable to Pwdn pull down
    19. always@(posedge clk_50M)
    20. begin
    21.   if(reset_n==1'b0) begin
    22. 	    cnt1<=0;
    23. 		 camera_pwnd_reg<=1'b1;  
    24.   end
    25.   else if(cnt1<18'h40000) begin
    26.        cnt1<=cnt1+1'b1;
    27.        camera_pwnd_reg<=1'b1;
    28.   end
    29.   else
    30.      camera_pwnd_reg<=1'b0;         
    31. end
    32.  
    33. //1.3ms, delay from pwdn low to resetb pull up
    34. always@(posedge clk_50M)
    35. begin
    36.   if(camera_pwnd_reg==1)  begin
    37. 	    cnt2<=0;
    38. 		 camera_rstn_reg<=1'b0;  
    39.   end
    40.   else if(cnt2<16'hffff) begin
    41.        cnt2<=cnt2+1'b1;
    42.        camera_rstn_reg<=1'b0;
    43.   end
    44.   else
    45.      camera_rstn_reg<=1'b1;         
    46. end
    48. //21ms, delay from resetb pul high to SCCB initialization
    49. always@(posedge clk_50M)
    50. begin
    51.   if(camera_rstn_reg==0) begin
    52.          cnt3<=0;
    53.          initial_en<=1'b0;
    54.   end
    55.   else if(cnt3<20'hfffff) begin
    56.         cnt3<=cnt3+1'b1;
    57.         initial_en<=1'b0;
    58.   end
    59.   else
    60.        initial_en<=1'b1;    
    61. end
    62.  
    63. endmodule

    sdram_vga_top 

    1. module sdram_vga_top
    2. (
    3. 	//global clock
    4. 	input			clk_vga,		//vga clock
    5. 	input			clk_ref,		//sdram ctrl clock
    6. 	input			clk_refout,		//sdram clock output
    7. 	input			rst_n,			//global reset
    8.  
    9. 	//sdram control
    10. 	output			sdram_clk,		//sdram clock
    11. 	output			sdram_cke,		//sdram clock enable
    12. 	output			sdram_cs_n,		//sdram chip select
    13. 	output			sdram_we_n,		//sdram write enable
    14. 	output			sdram_cas_n,	//sdram column address strobe
    15. 	output			sdram_ras_n,	//sdram row address strobe
    16. 	output			sdram_udqm,		//sdram data enable (H:8)
    17. 	output			sdram_ldqm,		//sdram data enable (L:8)
    18. 	output	[1:0]	sdram_ba,		//sdram bank address
    19. 	output	[11:0]	sdram_addr,		//sdram address
    20. 	inout	[15:0]	sdram_data,		//sdram data
    21. 		
    22. 	//lcd port
    23. 	output			lcd_dclk,		//lcd pixel clock			
    24. 	output			lcd_hs,			//lcd horizontal sync 
    25. 	output			lcd_vs,			//lcd vertical sync
    26. 	output			lcd_sync,		//lcd sync
    27. 	output			lcd_blank,		//lcd blank(L:blank)
    28. 	output	[4:0]	lcd_red,		//lcd red data
    29. 	output	[5:0]	lcd_green,		//lcd green data
    30. 	output	[4:0]	lcd_blue,		//lcd blue data
    31. 	
    32. 	//user interface
    33. 	input			clk_write,		//fifo write clock
    34. 	input			sys_we,			//fifo write enable
    35. 	input	[15:0]	sys_data_in,	//fifo data input
    36. 	output			sdram_init_done,//sdram init done
    37. 	input			frame_valid		//frame valid
    38. );
    39.  
    40.  
    41. //----------------------------------------------
    42. wire			sys_rd;        		//fifo read enable
    43. wire	[15:0]	sys_data_out;  		//fifo data output
    44. wire			lcd_framesync;		//lcd frame sync
    45. wire			frame_write_done;	//sdram write frame done
    46. wire			frame_read_done;	//sdram read frame done
    47. wire	[1:0]	wr_bank;			//sdram write bank
    48. wire	[1:0]	rd_bank;			//sdram read bank
    49. wire			wr_load;			//sdram write address reset
    50. wire			rd_load;			//sdram read address reset
    51. sdram_2fifo_top	u_sdram_2fifo_top
    52. (
    53. 	//global clock
    54. 	.clk_ref			(clk_ref),			//sdram	reference clock
    55. 	.clk_refout			(clk_refout),		//sdram clk	input 
    56. 	.clk_write			(clk_write),		//fifo data write clock
    57. 	.clk_read			(clk_vga),			//fifo data read clock
    58. 	.rst_n				(rst_n),			//global reset
    59. 	
    60. 	//sdram interface
    61. 	.sdram_clk			(sdram_clk),		//sdram clock	
    62. 	.sdram_cke			(sdram_cke),		//sdram clock enable	
    63. 	.sdram_cs_n			(sdram_cs_n),		//sdram chip select	
    64. 	.sdram_we_n			(sdram_we_n),		//sdram write enable	
    65. 	.sdram_ras_n		(sdram_ras_n),		//sdram column address strobe	
    66. 	.sdram_cas_n		(sdram_cas_n),		//sdram row address strobe	
    67. 	.sdram_ba			(sdram_ba),			//sdram data enable (H:8)    
    68. 	.sdram_addr			(sdram_addr),		//sdram data enable (L:8)	
    69. 	.sdram_data			(sdram_data),		//sdram bank address	
    70. 	.sdram_udqm			(sdram_udqm),		//sdram address	
    71. 	.sdram_ldqm			(sdram_ldqm),		//sdram data
    72. 	
    73. 	//user interface
    74. 	//burst and addr
    75. 	.wr_length			(9'd256),			//sdram write burst length
    76. 	.rd_length			(9'd256),			//sdram read burst length
    77. 	.wr_addr			({wr_bank,20'd0}),			//sdram start write address
    78. 	.wr_max_addr		({wr_bank,20'd307200}),		//sdram max write address
    79. 	.wr_load			(wr_load),			//sdram write address reset
    80. 	.rd_addr			({rd_bank,20'd0}),			//sdram start read address
    81. 	.rd_max_addr		({rd_bank,20'd307200}),		//sdram max read address
    82. 	.rd_load			(rd_load),			//sdram read address reset
    83. 	
    84. 	//dcfifo interface
    85. 	.sdram_init_done	(sdram_init_done),	//sdram init done
    86. 	.frame_write_done	(frame_write_done),	//sdram write one frame
    87. 	.frame_read_done	(frame_read_done),	//sdram read one frame
    88. 	.sys_we				(sys_we),			//fifo write enable
    89. 	.sys_data_in		(sys_data_in),		//fifo data input
    90. 	.sys_rd				(sys_rd),			//fifo read enable
    91. 	.sys_data_out		(sys_data_out),		//fifo data output
    92. 	.data_valid			(lcd_framesync)		//system data output enable
    93. );
    94.  
    95. //-----------------------------
    96. sdbank_switch	u_sdbank_switch
    97. (
    98. 	.clk				(clk_write),
    99. 	.rst_n				(rst_n),
    100. 	
    101. 	.bank_valid			(frame_valid),
    102. 	.frame_write_done	(frame_write_done),
    103. 	.frame_read_done	(frame_read_done),
    104. 	
    105. 	.wr_bank			(wr_bank),
    106. 	.rd_bank			(rd_bank),
    107. 	.wr_load			(wr_load),
    108. 	.rd_load			(rd_load)
    109. );
    110.  
    111. //---------------------------------
    112. //display on lcd
    113. wire	[10:0]	lcd_xpos;
    114. wire	[10:0]	lcd_ypos;
    115. wire	[15:0]	lcd_data;
    116. assign lcd_data = sys_data_out;
    117. /*
    118. lcd_display	U_lcd_display
    119. (
    120. 	.clk			(clk_vga),
    121. 	.rst_n			(rst_n),
    122.     
    123.     .alpha_data		(9'hC8),
    124. 	.lcd_xpos		(lcd_xpos),
    125. 	.lcd_ypos		(lcd_ypos),
    126. 	.lcd_data_in	(sys_data_out),	
    127. 	.lcd_data		(lcd_data)
    128. );
    129. */
    130. //-----------------------------
    131. //lcd driver top module
    132. lcd_top	u_lcd_top
    133. (
    134. 	//global clock
    135. 	.clk			(clk_vga),	
    136. 	.rst_n			(rst_n),	
    138. 	//lcd interface
    139. 	.lcd_blank		(lcd_blank),
    140. 	.lcd_sync		(lcd_sync),
    141. 	.lcd_dclk		(lcd_dclk),
    142. 	.lcd_hs			(lcd_hs),		
    143. 	.lcd_vs			(lcd_vs),	
    144. 	.lcd_en			(),	
    145. 	.lcd_rgb		({lcd_red, lcd_green ,lcd_blue}),
    147. 	//user interface
    148. 	.lcd_request	(sys_rd),
    149. 	.lcd_framesync	(lcd_framesync),
    150. 	.lcd_data		(lcd_data),
    151. 	.lcd_xpos		(lcd_xpos),
    152. 	.lcd_ypos		(lcd_ypos)
    153. );
    155. endmodule

     五、什么是DVP?

           DVP（Digital Video Port） 是传统的sensor输出接口，采用并行输出方式，d数据位宽有8bit、10bit、12bit、16bit，是CMOS电平信号（重点是非差分信号），PCLK最大速率为96MHz，接口如下图：

     DVP协议是摄像头中常用的协议，除了DVP协议摄像头中还有其他常用的协议如：MIPI、LVDS等协议,以实现标准图像数据流转换，其中摄像头8位数据转16位代码如下

    1. module cmos_8_16bit(
    2. 	input              rst,
    3. 	input              pclk,
    4. 	input [7:0]        pdata_i,
    5. 	input              de_i,
    6. 	output reg[15:0]   pdata_o,//转换成16位RGB565图像数据
    7. 	output reg         hblank,
    8. 	output reg         de_o
    9. );
    10. reg[7:0] pdata_i_d0;
    11. reg[11:0] x_cnt;
    12. always@(posedge pclk)
    13. begin
    14. 	pdata_i_d0 <= pdata_i;
    15. end
    16.  
    17. always@(posedge pclk or posedge rst)
    18. begin
    19. 	if(rst)
    20. 		x_cnt <= 12'd0;
    21. 	else if(de_i)
    22. 		x_cnt <= x_cnt + 12'd1;
    23. 	else
    24. 		x_cnt <= 12'd0;
    25. end
    27. always@(posedge pclk or posedge rst)
    28. begin
    29. 	if(rst)
    30. 		de_o <= 1'b0;
    31. 	else if(de_i && x_cnt[0])
    32. 		de_o <= 1'b1;
    33. 	else
    34. 		de_o <= 1'b0;
    35. end
    36.  
    37. always@(posedge pclk or posedge rst)
    38. begin
    39. 	if(rst)
    40. 		hblank <= 1'b0;
    41. 	else
    42. 		hblank <= de_i;
    43. end
    45. always@(posedge pclk or posedge rst)
    46. begin
    47. 	if(rst)
    48. 		pdata_o <= 16'd0;
    49. 	else if(de_i && x_cnt[0])
    50. 		pdata_o <= {pdata_i_d0,pdata_i};
    51. 	else
    52. 		pdata_o <= 16'd0;
    53. end
    55. endmodule

    六、摄像头写数据请求

    1. module cmos_write_req_gen(
    2. 	input              rst,
    3. 	input              pclk,
    4. 	input              cmos_vsync,
    5. 	output reg         write_req,
    6. 	output reg[1:0]    write_addr_index,
    7. 	output reg[1:0]    read_addr_index,
    8. 	input              write_req_ack
    9. );
    10. reg cmos_vsync_d0;
    11. reg cmos_vsync_d1;
    12. always@(posedge pclk or posedge rst)
    13. begin
    14. 	if(rst == 1'b1)
    15. 	begin
    16. 		cmos_vsync_d0 <= 1'b0;
    17. 		cmos_vsync_d1 <= 1'b0;
    18. 	end
    19. 	else
    20. 	begin
    21. 		cmos_vsync_d0 <= cmos_vsync;
    22. 		cmos_vsync_d1 <= cmos_vsync_d0;
    23. 	end
    24. end
    25. always@(posedge pclk or posedge rst)
    26. begin
    27. 	if(rst == 1'b1)
    28. 		write_req <= 1'b0;
    29. 	else if(cmos_vsync_d0 == 1'b1 && cmos_vsync_d1 == 1'b0)
    30. 		write_req <= 1'b1;
    31. 	else if(write_req_ack == 1'b1)
    32. 		write_req <= 1'b0;
    33. end
    34. always@(posedge pclk or posedge rst)
    35. begin
    36. 	if(rst == 1'b1)
    37. 		write_addr_index <= 2'b0;
    38. 	else if(cmos_vsync_d0 == 1'b1 && cmos_vsync_d1 == 1'b0)
    39. 		write_addr_index <= write_addr_index + 2'd1;
    40. end
    42. always@(posedge pclk or posedge rst)
    43. begin
    44. 	if(rst == 1'b1)
    45. 		read_addr_index <= 2'b0;
    46. 	else if(cmos_vsync_d0 == 1'b1 && cmos_vsync_d1 == 1'b0)
    47. 		read_addr_index <= write_addr_index;
    48. end
    49. endmodule

    七、顶层文件编写

    1. `timescale 1ns / 1ps
    2. module sdram_ov7670_vga
    3. (
    4. 	//global clock 50MHz
    5. 	//input			clk_27,			//27MHz
    6. 	input			CLOCK,	
    7. 	//input			rst_n,			//global reset
    8. 	
    9. 	//sdram control
    10. 	output			S_CLK,		//sdram clock
    11. 	output			S_CKE,		//sdram clock enable
    12. 	output			S_NCS,		//sdram chip select
    13. 	output			S_NWE,		//sdram write enable
    14. 	output			S_NCAS,	//sdram column address strobe
    15. 	output			S_NRAS,	//sdram row address strobe
    16. 	output[1:0] 	S_DQM,		//sdram data enable 
    17. 	output	[1:0]	S_BA,		//sdram bank address
    18. 	output	[12:0]	S_A,		//sdram address
    19. 	inout	[15:0]	S_DB,		//sdram data
    20. 	
    21. 	//VGA port			
    22. 	output			VGA_HSYNC,			//horizontal sync 
    23. 	output			VGA_VSYNC,			//vertical sync
    24. 	output	[15:0]	VGAD,		//VGA data
    25. 	
    26. 	//cmos interface
    27. 	output			CMOS_SCLK,		//cmos i2c clock
    28. 	inout			CMOS_SDAT,		//cmos i2c data
    29. 	input			CMOS_VSYNC,		//cmos vsync
    30. 	input			CMOS_HREF,		//cmos hsync refrence
    31. 	input			CMOS_PCLK,		//cmos pxiel clock
    32. 	output			CMOS_XCLK,		//cmos externl clock
    33. 	input	[7:0]	CMOS_DB,		//cmos data
    34. //	output			cmos_rst_n,		//cmos reset
    35. //	output			cmos_pwdn,		//cmos pwer down
    36.  
    37. 	output	[3:0]	LED		//led data input	
    38. );
    39. assign rst_n = 1'b1;
    40. //---------------------------------------------
    41. wire  clk_camera;
    42. wire	clk_vga;		//vga clock
    43. wire	clk_ref;		//sdram ctrl clock
    44. wire	clk_refout;		//sdram clock output
    45. wire	sys_rst_n;		//global reset
    46. system_ctrl	u_system_ctrl
    47. (
    48. 	.clk				(CLOCK),			//global clock  50MHZ
    49. 	.rst_n				(rst_n),		//external reset
    50. 	
    51. 	.sys_rst_n			(sys_rst_n),	//global reset
    52. 	.clk_c0				(clk_camera),	//13MHz
    53. 	.clk_c1				(clk_vga),		//25MHz
    54. 	.clk_c2				(clk_ref),	   //100MHz
    55. 	.clk_c3				(clk_refout)	//100MHz
    56. );
    57.  
    58.  
    59. //-----------------------------
    60. wire	[7:0]	I2C_RDATA;		//i2c register data
    61. wire	[7:0]	LUT_INDEX;		//lut index
    62. wire			Config_Done;	//I2C config done		
    63. I2C_AV_Config	u_I2C_AV_Config 
    64. (
    65. 	//Global clock
    66. 	.iCLK				(clk_vga),		//25MHz
    67. 	.iRST_N				(sys_rst_n),	//Global Reset
    68. 	
    69. 	//I2C Side
    70. 	.I2C_SCLK			(CMOS_SCLK),	//I2C CLOCK
    71. 	.I2C_SDAT			(CMOS_SDAT),	//I2C DATA
    72. 	
    73. 	//CMOS Signal
    74. 	.Config_Done		(Config_Done),	//I2C Config done
    75. 	.I2C_RDATA			(I2C_RDATA),	//CMOS ID
    76. 	.LUT_INDEX			()//(LUT_INDEX)		//ID Index
    77. );
    78. assign	led_data = I2C_RDATA;				//diaplay I2C_RDATA
    79. //-----------------------------------------------
    80. //Seg7_lut	u5	(	LUT_INDEX[7:4],	oSEG5	);	
    81. //Seg7_lut	u4	(	LUT_INDEX[3:0],	oSEG4	);
    82. //Seg7_lut	u1	(	I2C_RDATA[7:4],	oSEG1	);
    83. //Seg7_lut	u0	(	I2C_RDATA[3:0],	oSEG0	);
    84.  
    85. //-----------------------------------------------               
    86. wire			frame_valid;		//data valid, or address restart
    87. wire	[7:0]	cmos_fps_data;		//cmos frame rate
    88. CMOS_Capture	u_CMOS_Capture
    89. (
    90. 	//Global Clock
    91. 	.iCLK				(clk_camera),		//24MHz
    92. 	.iRST_N				(sys_rst_n),	//global reset
    93. 	
    94. 	//I2C Initilize Done
    95. 	.Init_Done			(Config_Done & sdram_init_done),	//Init Done
    96. 	
    97. 	//Sensor Interface
    98. 	.CMOS_RST_N			(),//(cmos_rst_n),	//cmos work state 
    99. 	.CMOS_PWDN			(),//(cmos_pwdn),	//cmos power on	
    100. 	.CMOS_XCLK			(CMOS_XCLK),		//cmos
    101. 	.CMOS_PCLK			(CMOS_PCLK),		//25MHz
    102. 	.CMOS_iDATA			(CMOS_DB),    	//CMOS Data
    103. 	.CMOS_VSYNC			(CMOS_VSYNC),  	 	//L: Vaild
    104. 	.CMOS_HREF			(CMOS_HREF), 		//H: Vaild
    105. 	                                    
    106. 	//Ouput Sensor Data                 
    107. 	.CMOS_oCLK			(sys_we),			//Data PCLK
    108. 	.CMOS_oDATA			(sys_data_in),  	//16Bits RGB
    109. 	.CMOS_VALID			(frame_valid),		//Data Enable
    110. 	.CMOS_FPS_DATA		()//(cmos_fps_data)		//cmos frame rate
    111. );
    112.  
    113. //Seg7_lut	u7	(	cmos_fps_data[7:4],	oSEG7	);	//fsp rate
    114. //Seg7_lut	u6	(	cmos_fps_data[3:0],	oSEG6	);	//fps rate
    115.  
    116.  
    117. //wire	[8:0]	alpha_data;					//alpha adjust data
    118. //assign	led_data = alpha_data;				//diaplay alpha data
    119. //alpha_control	u_alpha_control
    120. //(
    121. //	.clk				(clk_vga),			//vga clock
    122. //	.rst_n				(sys_rst_n),		//global reset
    123. //	
    124. //	.key_data			(key_data),			//key data
    125. //	.alpha_data			(alpha_data)		//aplha adjust data
    126. //);
    127.  
    128. //-------------------------------------
    129. //sdram vga ctrl system
    130. wire			sys_we;						//system data write enable
    131. wire	[15:0]	sys_data_in;				//system data input
    132. wire			sdram_init_done;			//sdram init done
    133. sdram_vga_top	u_sdram_vga_top
    134. (
    135. 	//global clock
    136. 	.clk_vga			(clk_vga),			//vga clock
    137. 	.clk_ref			(clk_ref),			//sdram ctrl clock
    138. 	.clk_refout			(clk_refout),		//sdram clock output
    139. 	.rst_n				(sys_rst_n),		//global reset
    140.  
    141. 	//sdram control
    142. 	.sdram_clk			(S_CLK),		//sdram clock
    143. 	.sdram_cke			(S_CKE),		//sdram clock enable
    144. 	.sdram_cs_n			(S_NCS),		//sdram chip select
    145. 	.sdram_we_n			(S_NWE),		//sdram write enable
    146. 	.sdram_cas_n		(S_NCAS),		//sdram column address strobe
    147. 	.sdram_ras_n		(S_NRAS),		//sdram row address strobe
    148. 	.sdram_udqm			(S_DQM[1]),		//sdram data enable (H:8)
    149. 	.sdram_ldqm			(S_DQM[0]),		//sdram data enable (L:8)
    150. 	.sdram_ba			(S_BA),			//sdram bank address
    151. 	.sdram_addr			(S_A),		//sdram address
    152. 	.sdram_data			(S_DB),		//sdram data
    153. 		
    154. 	//lcd port
    155. 	.lcd_dclk			(),			//lcd pixel clock			
    156. 	.lcd_hs				(VGA_HSYNC),			//lcd horizontal sync 
    157. 	.lcd_vs				(VGA_VSYNC),			//lcd vertical sync
    158. 	.lcd_sync			(),//(lcd_sync),			//lcd sync
    159. 	.lcd_blank			(),		//lcd blank(L:blank)
    160. 	.lcd_red			(VGAD[15:11]),			//lcd red data
    161. 	.lcd_green			(VGAD[10:5]),		//lcd green data
    162. 	.lcd_blue			(VGAD[4:0]),			//lcd blue data
    163. 	
    164. 	//user interface
    165. 	.clk_write			(CMOS_PCLK),			//fifo write clock
    166. 	.sys_we				(sys_we),			//fifo write enable
    167. 	.sys_data_in		(sys_data_in),		//fifo data input
    168. 	.sdram_init_done	(sdram_init_done),	//sdram init done
    169. 	.frame_valid		(frame_valid)		//frame valid
    170. );
    171.  
    172.  
    173. endmodule

    八、效果

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  • 原文地址：https://blog.csdn.net/mxh3600/article/details/126733682