RISC-V选项
-mbranch-cost=n
将分支的成本设置为大约 n 条指令。
-mplt
-mno-plt
允许或不允许使用PLT。默认是-mplt.
-mabi=ABI-string
指定整数和浮点调用约定。
如 ‘-march = rv64ifd -mabi = lp64d’
如，“-march = rv32if -mabi = ilp32d’
-mfdiv
-mno-fdiv
是否使用硬件浮点除法和平方根指令
-mdiv
-mno-div
是否使用硬件指令进行整数除法。
-march=ISA-string
子包括“rv64i’，‘rv32g’，'rv32e’和’rv32imaf’.
When-march=没有指定,则使用来自-mcpu.
-mcpu=processor-string
‘sifive-e20’，‘sifive-e21’，‘sifive-e24’，‘sifive-e31’，‘sifive-e34’，‘sifive-e76’，‘sifive-s21’，‘sifive-s51’，‘sifive-s54’，‘sifive-s76’，'sifive-u54’和’sifive-u74’.
-mtune=processor-string
‘rocket’，‘sifive-3-series’，‘sifive-5-series’，‘sifive-7-series’，‘size’，以及所有有效选项-mcpu=.
When-mtune=没有指定,则使用来自-mcpu, 默认为 ‘rocket’ 如果两者都没有指定。
-mpreferred-stack-boundary=num
尝试使堆栈边界与2对齐，以提高到 num 字节边界。如果-mpreferred-stack-boundary未指定,默认为4(16字节或128位)。
-msmall-data-limit=n
将小于 n 个字节的全局和静态数据放入一个特殊部分（在某些目标上）。
-msave-restore
-mno-save-restore
是否使用较小但较慢的使用库函数调用的序言和结尾代码
-mshorten-memrefs
-mno-shorten-memrefs
目前仅针对 32 位整数加载/存储。
-mstrict-align
-mno-strict-align
不产生或不产生不对齐的内存访问。
-mcmodel=medlow
生成中低码模型的代码。
-mcmodel=medany
生成中任何代码模型的代码。
-mexplicit-relocs
-mno-exlicit-relocs
,使用或不使用汇编器重定位操作符
-mrelax
-mno-relax
利用链接器松弛来减少实现符号地址所需的指令数量。
-memit-attribute
-mno-emit-attribute
额外信息记录到ELF对象中。需要 binutils 2.32。
-malign-data=type
控制GCC如何对齐数组，持的 type 值为“xlen’使用x寄存器宽度作为对齐值，
-mbig-endian
生成大端代码。
-mlittle-endian
生成小端代码。
-mstack-protector-guard=guard
-mstack-protector-guard-reg=reg
-mstack-protector-guard-offset=offset
使用canary at guard 生成堆栈保护代码
原始的在下面
RISC-V Options
The following table lists all available RISC-V specific options.
-fpic
-fPIC
Generate position-independent code
-fno-pic
Don’t generate position-independent code (default)
-march=ISA
Select the base isa, as specified by ISA. For example -march=rv32ima. If this option and the architecture attributes aren’t set, then assembler will check the default configure setting –with-arch=ISA.
-misa-spec=ISAspec
Select the default isa spec version. If the version of ISA isn’t set by -march, then assembler helps to set the version according to the default chosen spec. If this option isn’t set, then assembler will check the default configure setting –with-isa-spec=ISAspec.
-mpriv-spec=PRIVspec
Select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren’t set, then assembler will check the default configure setting –with-priv-spec=PRIVspec.
-mabi=ABI
Selects the ABI, which is either “ilp32” or “lp64”, optionally followed by “f”, “d”, or “q” to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none to indicate the soft-float calling convention. Also, “ilp32” can optionally be followed by “e” to indicate the RVE ABI, which is always soft-float.
-mrelax
Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default)
-mno-relax
Don’t do linker relaxations.
-march-attr
Generate the default contents for the riscv elf attribute section if the .attribute directives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.
-mno-arch-attr
Don’t generate the default riscv elf attribute section if the .attribute directives are not set.
-mcsr-check
Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions.
-mno-csr-check
Don’t do CSR checking.
-mlittle-endian
Generate code for a little endian machine.
-mbig-endian
Generate code for a big endian machine.