• 电力电子转战数字IC20220817day62——uvm入门实验4

    目录

    实验目标 

    存在问题 

     实验任务

    1.1移除driver中的mailbox句柄和do_drive()中用mailbox句柄通信的方式，用driver自带的seq_item_port通信；定义对应的uvm_sequencer

    1.2将generator中发送trans的任务改为底层sequence。将mcdf_base_test中的idle_reg()和write_reg()和read_reg()提取改为seq

    1.3在agent中声明、例化sequencer，并TLM连接到driver

    1.4去掉generator在mcdf_base_test中的声明+例化+连接到driver

    1.5去掉1.2中已经提取为seq的三个task

    1.6实现MCDF顶层的virtual sequencer

    1.7连接virtual sequencer和底层sequencer的句柄

    1.8将所有发送序列的顺序和组织等内容移植到mcdf_base_virtual_sequence，需要将mcdf_base_test::run_phase()发送序列的功能移植到mcdf_base_virtual_sequence；mcdf_base_test::run_phase()只需要挂载对应的顶层sequence

    1.9将原本test中产生和发送trans的任务提取到mcdf_data_consistence_basic_virtual_sequence中

    实验目标 

    存在问题 

    主要是关于sequence和sequencer的，见之前的笔记，没有太多改变。

     实验任务

    1.1移除driver中的mailbox句柄和do_drive()中用mailbox句柄通信的方式，用driver自带的seq_item_port通信；定义对应的uvm_sequencer

    首先是去掉mailbox的定义

    1.   class chnl_driver extends uvm_driver #(chnl_trans);
    2.     local virtual chnl_intf intf;
    3.    // mailbox #(chnl_trans) req_mb;
    4.    // mailbox #(chnl_trans) rsp_mb;

    在do_drive（）中将原来用mailbox通信的方式改为PORT通信。通过driver的seq_item_port端口调用get_next_item(req)获取req，由sequence的函数set_sequence_id设置id，所用id为req这个item调用get_sequence_id得到的；最后返回rsp。

    1.     task do_drive();
    2.       chnl_trans req, rsp;
    3.       @(posedge intf.rstn);
    4.       forever begin
    5. //        this.req_mb.get(req);
    6.         this.chnl_write(req);
    7.         void'($cast(rsp, req.clone()));
    8.         rsp.rsp = 1;
    9. //        this.rsp_mb.put(rsp);
    10.       end
    11.     endtask
    13.     task do_drive();
    14.       chnl_trans req, rsp;
    15.       @(posedge intf.rstn);
    16.       forever begin
    17.         //TODO-1.1 Use seq_item_port to get request item
    18.         seq_item_port.get_next_item(req);
    19.         this.chnl_write(req);
    20.         void'($cast(rsp, req.clone()));
    21.         rsp.rsp = 1;
    22.         //TODO-1.1 Use seq_item_port to put response item
    23.         rsp.set_sequence_id(req.get_sequence_id());
    24.         seq_item_port.item_done(rsp);
    25.       end
    26.     endtask

    定义sequencer，只需要注册和new函数即可，注意是参数类的要加参数#（）

    1.   class chnl_sequencer extends uvm_sequencer #(chnl_trans);
    2.     `uvm_component_utils(chnl_sequencer)
    3.     function new (string name = "chnl_sequencer", uvm_component parent);
    4.       super.new(name, parent);
    5.     endfunction
    6.   endclass: chnl_sequencer

    在fmt_pkg和reg_pkg中的操作完全相同。

    1.2将generator中发送trans的任务改为底层sequence。将mcdf_base_test中的idle_reg()和write_reg()和read_reg()提取改为seq

    改造generator：不需要mailbox；由于变成sequence，start任务变成body（）任务；将原来assert with做随机化约束变成`uvm_do_with；将mailbox通信改为seq通信；注意也是个参数类#（）

    1.   class chnl_data_sequence extends uvm_sequence #(chnl_trans);
    2.     rand int pkt_id = 0;
    3.     rand int ch_id = -1;
    4.     rand int data_nidles = -1;
    5.     rand int pkt_nidles = -1;
    6.     rand int data_size = -1;
    7.     rand int ntrans = 10;
    8.     `uvm_object_utils_begin(chnl_data_sequence)
    9.       `uvm_field_int(pkt_id, UVM_ALL_ON)
    10.       `uvm_field_int(ch_id, UVM_ALL_ON)
    11.       `uvm_field_int(data_nidles, UVM_ALL_ON)
    12.       `uvm_field_int(pkt_nidles, UVM_ALL_ON)
    13.       `uvm_field_int(data_size, UVM_ALL_ON)
    14.       `uvm_field_int(ntrans, UVM_ALL_ON)
    15.     `uvm_object_utils_end
    16.     `uvm_declare_p_sequencer(chnl_sequencer)
    17.     function new (string name = "chnl_data_sequence");
    18.       super.new(name);
    19.     endfunction
    20.  
    21.     task body();
    22.       repeat(ntrans) send_trans();
    23.     endtask
    24.  
    25.     task send_trans();
    26.       chnl_trans req, rsp;
    27.       `uvm_do_with(req, {local::ch_id >= 0 -> ch_id == local::ch_id; 
    28.                          local::pkt_id >= 0 -> pkt_id == local::pkt_id;
    29.                          local::data_nidles >= 0 -> data_nidles == local::data_nidles;
    30.                          local::pkt_nidles >= 0 -> pkt_nidles == local::pkt_nidles;
    31.                          local::data_size >0 -> data.size() == local::data_size; 
    32.                          })
    33.       this.pkt_id++;
    34.       `uvm_info(get_type_name(), req.sprint(), UVM_HIGH)
    35.       get_response(rsp);
    36.       `uvm_info(get_type_name(), rsp.sprint(), UVM_HIGH)
    37.       assert(rsp.rsp)
    38.         else $error("[RSPERR] %0t error response received!", $time);
    39.     endtask
    40.  
    41.     function void post_randomize();
    42.       string s;
    43.       s = {s, "AFTER RANDOMIZATION \n"};
    44.       s = {s, "=======================================\n"};
    45.       s = {s, "chnl_data_sequence object content is as below: \n"};
    46.       s = {s, super.sprint()};
    47.       s = {s, "=======================================\n"};
    48.       `uvm_info(get_type_name(), s, UVM_HIGH)
    49.     endfunction
    50.   endclass: chnl_data_sequence

    在fmt_pkg和reg_pkg中的操作完全相同。

    1. //原来在mcdf_base_test中的三个虚任务
    2.     virtual task idle_reg();
    3.       void'(reg_gen.randomize() with {cmd == `IDLE; addr == 0; data == 0;});
    4.       reg_gen.start();
    5.     endtask
    6.  
    7.     virtual task write_reg(bit[7:0] addr, bit[31:0] data);
    8.       void'(reg_gen.randomize() with {cmd == `WRITE; addr == local::addr; data == local::data;});
    9.       reg_gen.start();
    10.     endtask
    11.  
    12.     virtual task read_reg(bit[7:0] addr, output bit[31:0] data);
    13.       void'(reg_gen.randomize() with {cmd == `READ; addr == local::addr;});
    14.       reg_gen.start();
    15.       data = reg_gen.data;
    16.     endtask
    17.  
    18. //被替换成reg_pkg中的三个sequence，分别做约束，注册恶，new函数
    19.  
    20.   class idle_reg_sequence extends reg_base_sequence;
    21.     constraint cstr{
    22.       addr == 0;
    23.       cmd == `IDLE;
    24.       data == 0;
    25.     }
    26.     `uvm_object_utils(idle_reg_sequence)
    27.     function new (string name = "idle_reg_sequence");
    28.       super.new(name);
    29.     endfunction
    30.   endclass: idle_reg_sequence
    31.  
    32.   class write_reg_sequence extends reg_base_sequence;
    33.     constraint cstr{
    34.       cmd == `WRITE;
    35.     }
    36.     `uvm_object_utils(write_reg_sequence)
    37.     function new (string name = "write_reg_sequence");
    38.       super.new(name);
    39.     endfunction
    40.   endclass: write_reg_sequence
    41.  
    42.   class read_reg_sequence extends reg_base_sequence;
    43.     constraint cstr{
    44.       cmd == `READ;
    45.     }
    46.     `uvm_object_utils(read_reg_sequence)
    47.     function new (string name = "read_reg_sequence");
    48.       super.new(name);
    49.     endfunction
    50.   endclass: read_reg_sequence

    1.3在agent中声明、例化sequencer，并TLM连接到driver

    1.   class chnl_agent extends uvm_agent;
    2.     chnl_driver driver;
    3.     chnl_monitor monitor;
    4.     //声明sequencer
    5.     chnl_sequencer sequencer;
    6.     local virtual chnl_intf vif;
    7.  
    8.     `uvm_component_utils(chnl_agent)
    9.  
    10.     function new(string name = "chnl_agent", uvm_component parent);
    11.       super.new(name, parent);
    12.     endfunction
    13.  
    14.     function void build_phase(uvm_phase phase);
    15.       super.build_phase(phase);
    16.       driver = chnl_driver::type_id::create("driver", this);
    17.       monitor = chnl_monitor::type_id::create("monitor", this);
    18.       //例化sequencer
    19.       sequencer = chnl_sequencer::type_id::create("sequencer", this);
    20.     endfunction
    21.  
    22.     function void connect_phase(uvm_phase phase);
    23.       super.connect_phase(phase);
    24.       //连接driver和sequencer
    25.       driver.seq_item_port.connect(sequencer.seq_item_export);
    26.     endfunction
    27.  
    28.     function void set_interface(virtual chnl_intf vif);
    29.       this.vif = vif;
    30.       driver.set_interface(vif);
    31.       monitor.set_interface(vif);
    32.     endfunction
    33.   endclass: chnl_agent

    在fmt_pkg和reg_pkg中的操作完全相同。

    1.4去掉generator在mcdf_base_test中的声明+例化+连接到driver

    1.5去掉1.2中已经提取为seq的三个task

    1.6实现MCDF顶层的virtual sequencer

    virtual sequencer包含所有底层sequencer的句柄

    1.   class mcdf_virtual_sequencer extends uvm_sequencer;
    2.     reg_sequencer reg_sqr;
    3.     fmt_sequencer fmt_sqr;
    4.     chnl_sequencer chnl_sqrs[3];
    5.     `uvm_component_utils(mcdf_virtual_sequencer)
    6.     function new (string name = "mcdf_virtual_sequencer", uvm_component parent);
    7.       super.new(name, parent);
    8.     endfunction
    9.   endclass

    1.7连接virtual sequencer和底层sequencer的句柄

    1.   class mcdf_env extends uvm_env;
    2.     chnl_agent chnl_agts[3];
    3.     reg_agent reg_agt;
    4.     fmt_agent fmt_agt;
    5.     mcdf_checker chker;
    6.     mcdf_coverage cvrg;
    7.     //声明
    8.     mcdf_virtual_sequencer virt_sqr;
    9.  
    10.     `uvm_component_utils(mcdf_env)
    11.  
    12.     function new (string name = "mcdf_env", uvm_component parent);
    13.       super.new(name, parent);
    14.     endfunction
    15.  
    16.     function void build_phase(uvm_phase phase);
    17.       super.build_phase(phase);
    18.       this.chker = mcdf_checker::type_id::create("chker", this);
    19.       foreach(chnl_agts[i]) begin
    20.         this.chnl_agts[i] = chnl_agent::type_id::create($sformatf("chnl_agts[%0d]",i), this);
    21.       end
    22.       this.reg_agt = reg_agent::type_id::create("reg_agt", this);
    23.       this.fmt_agt = fmt_agent::type_id::create("fmt_agt", this);
    24.       this.cvrg = mcdf_coverage::type_id::create("cvrg", this);
    25.       //例化
    26.       virt_sqr = mcdf_virtual_sequencer::type_id::create("virt_sqr", this);
    27.     endfunction
    28.  
    29.     function void connect_phase(uvm_phase phase);
    30.       super.connect_phase(phase);
    31.       chnl_agts[0].monitor.mon_bp_port.connect(chker.chnl0_bp_imp);
    32.       chnl_agts[1].monitor.mon_bp_port.connect(chker.chnl1_bp_imp);
    33.       chnl_agts[2].monitor.mon_bp_port.connect(chker.chnl2_bp_imp);
    34.       reg_agt.monitor.mon_bp_port.connect(chker.reg_bp_imp);
    35.       fmt_agt.monitor.mon_bp_port.connect(chker.fmt_bp_imp);
    36.       //和底层的sequencer连接起来
    37.       virt_sqr.reg_sqr = reg_agt.sequencer;
    38.       virt_sqr.fmt_sqr = fmt_agt.sequencer;
    39.       foreach(virt_sqr.chnl_sqrs[i]) virt_sqr.chnl_sqrs[i] = chnl_agts[i].sequencer;
    40.     endfunction
    41.   endclass: mcdf_env

    1.8将所有发送序列的顺序和组织等内容移植到mcdf_base_virtual_sequence，需要将mcdf_base_test::run_phase()发送序列的功能移植到mcdf_base_virtual_sequence；mcdf_base_test::run_phase()只需要挂载对应的顶层sequence

    就是对应virtual sequencer的顶层virtual sequence。

    1.   class mcdf_base_virtual_sequence extends uvm_sequence;
    2. //对应virtual sequencer的顶层virtual sequence
    3.     idle_reg_sequence idle_reg_seq;
    4.     write_reg_sequence write_reg_seq;
    5.     read_reg_sequence read_reg_seq;
    6.     chnl_data_sequence chnl_data_seq;
    7.     fmt_config_sequence fmt_config_seq;
    8.  
    9.     `uvm_object_utils(mcdf_base_virtual_sequence)
    10.     `uvm_declare_p_sequencer(mcdf_virtual_sequencer)
    11.  
    12.     function new (string name = "mcdf_base_virtual_sequence");
    13.       super.new(name);
    14.     endfunction
    15.  
    16.     virtual task body();
    17.       `uvm_info(get_type_name(), "=====================STARTED=====================", UVM_LOW)
    18.       this.do_reg();
    19.       this.do_formatter();
    20.       this.do_data();
    21.       `uvm_info(get_type_name(), "=====================FINISHED=====================", UVM_LOW)
    22.     endtask
    23.  
    24.     // do register configuration
    25.     virtual task do_reg();
    26.     endtask
    27.  
    28.     // do external formatter down stream slave configuration
    29.     virtual task do_formatter();
    30.     endtask
    31.  
    32.     // do data transition from 3 channel slaves
    33.     virtual task do_data();
    34.     endtask
    35.  
    36.     virtual function bit diff_value(int val1, int val2, string id = "value_compare");
    37.       if(val1 != val2) begin
    38.         `uvm_error("[CMPERR]", $sformatf("ERROR! %s val1 %8x != val2 %8x", id, val1, val2)) 
    39.         return 0;
    40.       end
    41.       else begin
    42.         `uvm_info("[CMPSUC]", $sformatf("SUCCESS! %s val1 %8x == val2 %8x", id, val1, val2), UVM_LOW)
    43.         return 1;
    44.       end
    45.     endfunction
    46.   endclass

    而在mcdf_base_test::run_phase()中只需要运行对应的虚方法

    1.     task run_phase(uvm_phase phase);
    2.       phase.raise_objection(this);
    3.       this.run_top_virtual_sequence();
    4.       phase.drop_objection(this);
    5.     endtask
    6.  
    7.     virtual task run_top_virtual_sequence();
    8.     endtask

    在不同的test中用继承的字方法来自定义所需要的的seq

    1.     task run_top_virtual_sequence();
    2.       mcdf_data_consistence_basic_virtual_sequence top_seq = new();
    3.       top_seq.start(env.virt_sqr);
    4.     endtask
    5.  
    6.  
    7.     task run_top_virtual_sequence();
    8.       mcdf_full_random_virtual_sequence top_seq = new();
    9.       top_seq.start(env.virt_sqr);
    10.     endtask

    1.9将原本test中产生和发送trans的任务提取到mcdf_data_consistence_basic_virtual_sequence中

    1.   class mcdf_data_consistence_basic_virtual_sequence extends mcdf_base_virtual_sequence;
    2.     `uvm_object_utils(mcdf_data_consistence_basic_virtual_sequence)
    3.     function new (string name = "mcdf_data_consistence_basic_virtual_sequence");
    4.       super.new(name);
    5.     endfunction
    6.     task do_reg();
    7.       bit[31:0] wr_val, rd_val;
    8.       // slv0 with len=8,  prio=0, en=1
    9.       wr_val = (1<<3)+(0<<1)+1;
    10.       `uvm_do_on_with(write_reg_seq, p_sequencer.reg_sqr, {addr == `SLV0_RW_ADDR; data == wr_val;})
    11.       `uvm_do_on_with(read_reg_seq, p_sequencer.reg_sqr, {addr == `SLV0_RW_ADDR;})
    12.       rd_val = read_reg_seq.data;
    13.       void'(this.diff_value(wr_val, rd_val, "SLV0_WR_REG"));
    15.       // slv1 with len=16, prio=1, en=1
    16.       wr_val = (2<<3)+(1<<1)+1;
    17.       `uvm_do_on_with(write_reg_seq, p_sequencer.reg_sqr, {addr == `SLV1_RW_ADDR; data == wr_val;})
    18.       `uvm_do_on_with(read_reg_seq, p_sequencer.reg_sqr, {addr == `SLV1_RW_ADDR;})
    19.       rd_val = read_reg_seq.data;
    20.       void'(this.diff_value(wr_val, rd_val, "SLV1_WR_REG"));
    21.  
    22.       // slv2 with len=32, prio=2, en=1
    23.       wr_val = (3<<3)+(2<<1)+1;
    24.       `uvm_do_on_with(write_reg_seq, p_sequencer.reg_sqr, {addr == `SLV2_RW_ADDR; data == wr_val;})
    25.       `uvm_do_on_with(read_reg_seq, p_sequencer.reg_sqr, {addr == `SLV2_RW_ADDR;})
    26.       rd_val = read_reg_seq.data;
    27.       void'(this.diff_value(wr_val, rd_val, "SLV2_WR_REG"));
    29.       // send IDLE command
    30.       `uvm_do_on(idle_reg_seq, p_sequencer.reg_sqr)
    31.     endtask
    32.     task do_formatter();
    33.       `uvm_do_on_with(fmt_config_seq, p_sequencer.fmt_sqr, {fifo == LONG_FIFO; bandwidth == HIGH_WIDTH;})
    34.     endtask
    35.     task do_data();
    36.       fork
    37.         `uvm_do_on_with(chnl_data_seq, p_sequencer.chnl_sqrs[0], {ntrans==100; ch_id==0; data_nidles==0; pkt_nidles==1; data_size==8; })
    38.         `uvm_do_on_with(chnl_data_seq, p_sequencer.chnl_sqrs[1], {ntrans==100; ch_id==1; data_nidles==1; pkt_nidles==4; data_size==16;})
    39.         `uvm_do_on_with(chnl_data_seq, p_sequencer.chnl_sqrs[2], {ntrans==100; ch_id==2; data_nidles==2; pkt_nidles==8; data_size==32;})
    40.       join
    41.       #10us; // wait until all data haven been transfered through MCDF
    42.     endtask
    43.   endclass: mcdf_data_consistence_basic_virtual_sequence

    原本在test中的处理trans的三个任务早已在1.2中被提取为sequence（idle_reg_seq，write_reg_seq，read_reg_seq ）

    现在的test只剩下注册，new函数，运行顶层virtual seq的任务了

    1.   class mcdf_data_consistence_basic_test extends mcdf_base_test;
    2.  
    3.     `uvm_component_utils(mcdf_data_consistence_basic_test)
    4.  
    5.     function new(string name = "mcdf_data_consistence_basic_test", uvm_component parent);
    6.       super.new(name, parent);
    7.     endfunction
    8.  
    9.     task run_top_virtual_sequence();
    10.       mcdf_data_consistence_basic_virtual_sequence top_seq = new();
    11.       top_seq.start(env.virt_sqr);
    12.     endtask
    13.   endclass: mcdf_data_consistence_basic_test

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  • 原文地址：https://blog.csdn.net/weixin_39668316/article/details/126393986