• Amlogic S905X4 平台上针对HDMI TX（OUT） CEC操作

    common/drivers/amlogic/media/cec/hdmi_tx_cec_20.h

    1. /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
    2. /*
    3.  * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
    4.  */
    5.  
    6. #ifndef _TX_CEC_H_
    7. #define _TX_CEC_H_
    8.  
    9. #define CEC0_LOG_ADDR 4 /* MBX logical address */
    10. #define TV_CEC_INTERVAL     (HZ * 3)
    11.  
    12. #define CEC_VERSION     "v1.3"
    13. #define _RX_DATA_BUF_SIZE_ 16
    14.  
    15. #define AO_CEC  /* for switch between aocec and hdmi cec2.0 */
    16.  
    17. #define MAX_MSG           16
    18. #define MAX_NUM_OF_DEV    16
    19.  
    20. enum _cec_log_dev_addr_e {
    21. 	CEC_TV_ADDR					= 0x00,
    22. 	CEC_RECORDING_DEVICE_1_ADDR,
    23. 	CEC_RECORDING_DEVICE_2_ADDR,
    24. 	CEC_TUNER_1_ADDR,
    25. 	CEC_PLAYBACK_DEVICE_1_ADDR,
    26. 	CEC_AUDIO_SYSTEM_ADDR,
    27. 	CEC_TUNER_2_ADDR,
    28. 	CEC_TUNER_3_ADDR,
    29. 	CEC_PLAYBACK_DEVICE_2_ADDR,
    30. 	CEC_RECORDING_DEVICE_3_ADDR,
    31. 	CEC_TUNER_4_ADDR,
    32. 	CEC_PLAYBACK_DEVICE_3_ADDR,
    33. 	CEC_RESERVED_1_ADDR,
    34. 	CEC_RESERVED_2_ADDR,
    35. 	CEC_FREE_USE_ADDR,
    36. 	CEC_UNREGISTERED_ADDR
    37. };
    38.  
    39. #define CEC_BROADCAST_ADDR CEC_UNREGISTERED_ADDR
    40.  
    41. #define CEC_TV                   (BIT(0))
    42. #define CEC_RECORDING_DEVICE_1   (BIT(1))
    43. #define CEC_RECORDING_DEVICE_2   (BIT(2))
    44. #define CEC_TUNER_1              (BIT(3))
    45. #define CEC_PLAYBACK_DEVICE_1    (BIT(4))
    46. #define CEC_AUDIO_SYSTEM         (BIT(5))
    47. #define CEC_TUNER_2              (BIT(6))
    48. #define CEC_TUNER_3              (BIT(7))
    49. #define CEC_PLAYBACK_DEVICE_2    (BIT(8))
    50. #define CEC_RECORDING_DEVICE_3   (BIT(9))
    51. #define CEC_TUNER_4              (BIT(10))
    52. #define CEC_PLAYBACK_DEVICE_3    (BIT(11))
    53. #define CEC_RESERVED_1           (BIT(12))
    54. #define CEC_RESERVED_2           (BIT(13))
    55. #define CEC_FREE_USE             (BIT(14))
    56. #define CEC_UNREGISTERED         (BIT(15))
    57.  
    58. #define CEC_DISPLAY_DEVICE       (CEC_TV | CEC_FREE_USE)
    59. #define CEC_RECORDING_DEVICE     (CEC_RECORDING_DEVICE_1 \
    60. 	    | CEC_RECORDING_DEVICE_2 | CEC_RECORDING_DEVICE_3)
    61. #define CEC_PLAYBACK_DEVICE      (CEC_PLAYBACK_DEVICE_1 \
    62. 	    | CEC_PLAYBACK_DEVICE_2 | CEC_PLAYBACK_DEVICE_3)
    63. #define CEC_TUNER_DEVICE         (CEC_TUNER_1 | CEC_TUNER_2 \
    64. 	    | CEC_TUNER_3 | CEC_TUNER_4)
    65. #define CEC_AUDIO_SYSTEM_DEVICE  (CEC_AUDIO_SYSTEM)
    66.  
    67. #define CEC_IOC_MAGIC                   'C'
    68. #define CEC_IOC_GET_PHYSICAL_ADDR       _IOR(CEC_IOC_MAGIC, 0x00, uint16_t)
    69. #define CEC_IOC_GET_VERSION             _IOR(CEC_IOC_MAGIC, 0x01, int)
    70. #define CEC_IOC_GET_VENDOR_ID           _IOR(CEC_IOC_MAGIC, 0x02, uint32_t)
    71. #define CEC_IOC_GET_PORT_INFO           _IOR(CEC_IOC_MAGIC, 0x03, int)
    72. #define CEC_IOC_GET_PORT_NUM            _IOR(CEC_IOC_MAGIC, 0x04, int)
    73. #define CEC_IOC_GET_SEND_FAIL_REASON    _IOR(CEC_IOC_MAGIC, 0x05, uint32_t)
    74. #define CEC_IOC_SET_OPTION_WAKEUP       _IOW(CEC_IOC_MAGIC, 0x06, uint32_t)
    75. #define CEC_IOC_SET_OPTION_ENALBE_CEC   _IOW(CEC_IOC_MAGIC, 0x07, uint32_t)
    76. #define CEC_IOC_SET_OPTION_SYS_CTRL     _IOW(CEC_IOC_MAGIC, 0x08, uint32_t)
    77. #define CEC_IOC_SET_OPTION_SET_LANG     _IOW(CEC_IOC_MAGIC, 0x09, uint32_t)
    78. #define CEC_IOC_GET_CONNECT_STATUS      _IOR(CEC_IOC_MAGIC, 0x0A, uint32_t)
    79. #define CEC_IOC_ADD_LOGICAL_ADDR        _IOW(CEC_IOC_MAGIC, 0x0B, uint32_t)
    80. #define CEC_IOC_CLR_LOGICAL_ADDR        _IOW(CEC_IOC_MAGIC, 0x0C, uint32_t)
    81. #define CEC_IOC_SET_DEV_TYPE            _IOW(CEC_IOC_MAGIC, 0x0D, uint32_t)
    82. #define CEC_IOC_SET_ARC_ENABLE          _IOW(CEC_IOC_MAGIC, 0x0E, uint32_t)
    83. #define CEC_IOC_SET_AUTO_DEVICE_OFF     _IOW(CEC_IOC_MAGIC, 0x0F, uint32_t)
    84. #define CEC_IOC_GET_BOOT_ADDR           _IOW(CEC_IOC_MAGIC, 0x10, uint32_t)
    85. #define CEC_IOC_GET_BOOT_REASON         _IOW(CEC_IOC_MAGIC, 0x11, uint32_t)
    86. #define CEC_IOC_SET_FREEZE_MODE         _IOW(CEC_IOC_MAGIC, 0x12, uint32_t)
    87. #define CEC_IOC_GET_BOOT_PORT           _IOW(CEC_IOC_MAGIC, 0x13, uint32_t)
    88. #define CEC_IOC_SET_DEBUG_EN		_IOW(CEC_IOC_MAGIC, 0x14, uint32_t)
    89.  
    90. enum cec_tx_ret {
    91. 	CEC_FAIL_NONE = 0,
    92. 	CEC_FAIL_NACK = 1,
    93. 	CEC_FAIL_BUSY = 2,
    94. 	CEC_FAIL_OTHER = 3
    95. };
    96.  
    97. enum hdmi_port_type {
    98. 	HDMI_INPUT = 0,
    99. 	HDMI_OUTPUT = 1
    100. };
    101.  
    102. struct hdmi_port_info {
    103. 	int type;
    104. 	/* Port ID should start from 1 which corresponds to HDMI "port 1". */
    105. 	int port_id;
    106. 	int cec_supported;
    107. 	int arc_supported;
    108. 	u16 physical_address;
    109. };
    110.  
    111. enum cec_dev_type_addr {
    112. 	CEC_DISPLAY_DEVICE_TYPE = 0x0,
    113. 	CEC_RECORDING_DEVICE_TYPE,
    114. 	CEC_RESERVED_DEVICE_TYPE,
    115. 	CEC_TUNER_DEVICE_TYPE,
    116. 	CEC_PLAYBACK_DEVICE_TYPE,
    117. 	CEC_AUDIO_SYSTEM_DEVICE_TYPE,
    118. 	CEC_UNREGISTERED_DEVICE_TYPE,
    119. };
    120.  
    121. enum cec_feature_abort_e {
    122. 	CEC_UNRECONIZED_OPCODE = 0x0,
    123. 	CEC_NOT_CORRECT_MODE_TO_RESPOND,
    124. 	CEC_CANNOT_PROVIDE_SOURCE,
    125. 	CEC_INVALID_OPERAND,
    126. 	CEC_REFUSED,
    127. 	CEC_UNABLE_TO_DETERMINE,
    128. };
    129.  
    130. /*
    131.  * CEC OPCODES
    132.  */
    133. #define CEC_OC_ABORT_MESSAGE                     0xFF
    134. #define CEC_OC_ACTIVE_SOURCE                     0x82
    135. #define CEC_OC_CEC_VERSION                       0x9E
    136. #define CEC_OC_CLEAR_ANALOGUE_TIMER              0x33
    137. #define CEC_OC_CLEAR_DIGITAL_TIMER               0x99
    138. #define CEC_OC_CLEAR_EXTERNAL_TIMER              0xA1
    139. #define CEC_OC_DECK_CONTROL                      0x42
    140. #define CEC_OC_DECK_STATUS                       0x1B
    141. #define CEC_OC_DEVICE_VENDOR_ID                  0x87
    142. #define CEC_OC_FEATURE_ABORT                     0x00
    143. #define CEC_OC_GET_CEC_VERSION                   0x9F
    144. #define CEC_OC_GET_MENU_LANGUAGE                 0x91
    145. #define CEC_OC_GIVE_AUDIO_STATUS                 0x71
    146. #define CEC_OC_GIVE_DECK_STATUS                  0x1A
    147. #define CEC_OC_GIVE_DEVICE_POWER_STATUS          0x8F
    148. #define CEC_OC_GIVE_DEVICE_VENDOR_ID             0x8C
    149. #define CEC_OC_GIVE_OSD_NAME                     0x46
    150. #define CEC_OC_GIVE_PHYSICAL_ADDRESS             0x83
    151. #define CEC_OC_GIVE_SYSTEM_AUDIO_MODE_STATUS     0x7D
    152. #define CEC_OC_GIVE_TUNER_DEVICE_STATUS          0x08
    153. #define CEC_OC_IMAGE_VIEW_ON                     0x04
    154. #define CEC_OC_INACTIVE_SOURCE                   0x9D
    155. #define CEC_OC_MENU_REQUEST                      0x8D
    156. #define CEC_OC_MENU_STATUS                       0x8E
    157. #define CEC_OC_PLAY                              0x41
    158. #define CEC_OC_POLLING_MESSAGE                   0xFC
    159. #define CEC_OC_RECORD_OFF                        0x0B
    160. #define CEC_OC_RECORD_ON                         0x09
    161. #define CEC_OC_RECORD_STATUS                     0x0A
    162. #define CEC_OC_RECORD_TV_SCREEN                  0x0F
    163. #define CEC_OC_REPORT_AUDIO_STATUS               0x7A
    164. #define CEC_OC_REPORT_PHYSICAL_ADDRESS           0x84
    165. #define CEC_OC_REPORT_POWER_STATUS               0x90
    166. #define CEC_OC_REQUEST_ACTIVE_SOURCE             0x85
    167. #define CEC_OC_ROUTING_CHANGE                    0x80
    168. #define CEC_OC_ROUTING_INFORMATION               0x81
    169. #define CEC_OC_SELECT_ANALOGUE_SERVICE           0x92
    170. #define CEC_OC_SELECT_DIGITAL_SERVICE            0x93
    171. #define CEC_OC_SET_ANALOGUE_TIMER                0x34
    172. #define CEC_OC_SET_AUDIO_RATE                    0x9A
    173. #define CEC_OC_SET_DIGITAL_TIMER                 0x97
    174. #define CEC_OC_SET_EXTERNAL_TIMER                0xA2
    175. #define CEC_OC_SET_MENU_LANGUAGE                 0x32
    176. #define CEC_OC_SET_OSD_NAME                      0x47
    177. #define CEC_OC_SET_OSD_STRING                    0x64
    178. #define CEC_OC_SET_STREAM_PATH                   0x86
    179. #define CEC_OC_SET_SYSTEM_AUDIO_MODE             0x72
    180. #define CEC_OC_SET_TIMER_PROGRAM_TITLE           0x67
    181. #define CEC_OC_STANDBY                           0x36
    182. #define CEC_OC_SYSTEM_AUDIO_MODE_REQUEST         0x70
    183. #define CEC_OC_SYSTEM_AUDIO_MODE_STATUS          0x7E
    184. #define CEC_OC_TEXT_VIEW_ON                      0x0D
    185. #define CEC_OC_TIMER_CLEARED_STATUS              0x43
    186. #define CEC_OC_TIMER_STATUS                      0x35
    187. #define CEC_OC_TUNER_DEVICE_STATUS               0x07
    188. #define CEC_OC_TUNER_STEP_DECREMENT              0x06
    189. #define CEC_OC_TUNER_STEP_INCREMENT              0x05
    190. #define CEC_OC_USER_CONTROL_PRESSED              0x44
    191. #define CEC_OC_USER_CONTROL_RELEASED             0x45
    192. #define CEC_OC_VENDOR_COMMAND                    0x89
    193. #define CEC_OC_VENDOR_COMMAND_WITH_ID            0xA0
    194. #define CEC_OC_VENDOR_REMOTE_BUTTON_DOWN         0x8A
    195. #define CEC_OC_VENDOR_REMOTE_BUTTON_UP           0x8B
    196.  
    197. /* cec global struct */
    198.  
    199. enum cec_node_status_e {
    200. 	STATE_UNKNOWN = 0x00,
    201. 	STATE_START,
    202. 	STATE_STOP
    203. };
    204.  
    205. enum cec_power_status_e {
    206. 	CEC_PW_POWER_ON = 0x00,
    207. 	CEC_PW_STANDBY,
    208. 	CEC_PW_TRANS_STANDBY_TO_ON,
    209. 	CEC_PW_TRANS_ON_TO_STANDBY,
    210. };
    211.  
    212. enum status_req_mode_e {
    213. 	STATUS_REQ_ON = 1,
    214. 	STATUS_REQ_OFF,
    215. 	STATUS_REQ_ONCE,
    216. };
    217.  
    218. enum deck_info_e {
    219. 	DECK_UNKNOWN_STATUS = 0,
    220. 	DECK_PLAY = 0X11,
    221. 	DECK_RECORD,
    222. 	DECK_PLAY_REVERSE,
    223. 	DECK_STILL,
    224. 	DECK_SLOW,
    225. 	DECK_SLOW_REVERSE,
    226. 	DECK_FAST_FORWARD,
    227. 	DECK_FAST_REVERSE,
    228. 	DECK_NO_MEDIA,
    229. 	DECK_STOP,
    230. 	DECK_SKIP_FORWARD_WIND,
    231. 	DECK_SKIP_REVERSE_REWIND,
    232. 	DECK_INDEX_SEARCH_FORWARD,
    233. 	DECK_INDEX_SEARCH_REVERSE,
    234. 	DECK_OTHER_STATUS,
    235. };
    236.  
    237. enum deck_cnt_mode_e {
    238. 	DECK_CNT_SKIP_FORWARD_WIND = 1,
    239. 	DECK_CNT_SKIP_REVERSE_REWIND,
    240. 	DECK_CNT_STOP,
    241. 	DECK_CNT_EJECT,
    242. };
    243.  
    244. enum play_mode_e {
    245. 	PLAY_FORWARD = 0X24,
    246. 	PLAY_REVERSE = 0X20,
    247. 	PLAY_STILL = 0X25,
    248. 	FAST_FORWARD_MIN_SPEED = 0X05,
    249. 	FAST_FORWARD_MEDIUM_SPEED = 0X06,
    250. 	FAST_FORWARD_MAX_SPEED = 0X07,
    251. 	FAST_REVERSE_MIN_SPEED = 0X09,
    252. 	FAST_REVERSE_MEDIUM_SPEED = 0X0A,
    253. 	FAST_REVERSE_MAX_SPEED = 0X0B,
    254. 	SLOW_FORWARD_MIN_SPEED = 0X15,
    255. 	SLOW_FORWARD_MEDIUM_SPEED = 0X16,
    256. 	SLOW_FORWARD_MAX_SPEED = 0X17,
    257. 	SLOW_REVERSE_MIN_SPEED = 0X19,
    258. 	SLOW_REVERSE_MEDIUM_SPEED = 0X1A,
    259. 	SLOW_REVERSE_MAX_SPEED = 0X1B,
    260. };
    261.  
    262. enum cec_version_e {
    263. 	CEC_VERSION_11 = 0,
    264. 	CEC_VERSION_12,
    265. 	CEC_VERSION_12A,
    266. 	CEC_VERSION_13,
    267. 	CEC_VERSION_13A,
    268. 	CEC_VERSION_14A,
    269. 	CEC_VERSION_20,
    270. };
    271.  
    272. #define INFO_MASK_CEC_VERSION                (BIT(0))
    273. #define INFO_MASK_VENDOR_ID                  (BIT(1))
    274. #define INFO_MASK_DEVICE_TYPE                (BIT(2))
    275. #define INFO_MASK_POWER_STATUS               (BIT(3))
    276. #define INFO_MASK_PHYSICAL_ADDRESS           (BIT(4))
    277. #define INFO_MASK_LOGIC_ADDRESS              (BIT(5))
    278. #define INFO_MASK_OSD_NAME                   (BIT(6))
    279. #define INFO_MASK_MENU_STATE                 (BIT(7))
    280. #define INFO_MASK_MENU_LANGUAGE              (BIT(8))
    281. #define INFO_MASK_DECK_INfO                  (BIT(9))
    282. #define INFO_MASK_PLAY_MODE                  (BIT(10))
    283.  
    284. /*
    285.  * only for 1 tx device
    286.  */
    287. struct cec_global_info_t {
    288. 	dev_t dev_no;
    289. 	atomic_t open_count;
    290. 	unsigned int hal_ctl;			/* message controlled by hal */
    291. 	unsigned int vendor_id:24;
    292. 	unsigned int menu_lang;
    293. 	unsigned int cec_version;
    294. 	unsigned char power_status;
    295. 	unsigned char log_addr;
    296. 	unsigned int addr_enable;
    297. 	unsigned char menu_status;
    298. 	unsigned char osd_name[16];
    299. 	struct input_dev *remote_cec_dev;	/* cec input device */
    300. 	struct hdmitx_dev *hdmitx_device;
    301. };
    302.  
    303. enum cec_device_menu_state_e {
    304. 	DEVICE_MENU_ACTIVE = 0,
    305. 	DEVICE_MENU_INACTIVE,
    306. };
    307.  
    308. #endif

    具体操作对应关系：

    如以下命令

    echo 0x40 0x04 > /sys/class/cec/cmd  (To turn the TV on)
    echo 0x40 0x36 > /sys/class/cec/cmd  (To turn the TV off)
    echo 0x40 0x8F > /sys/class/cec/cmd      (CEC_OC_GIVE_DEVICE_POWER_STATUS)

    echo 0x40  VALUE  > /sys/class/cec/cmd

    VALUE 对应以下绿色框起来的部分

     操作命令后，可以使用命令

    cat /sys/class/cec/dump_reg    //读取CEC 寄存器状态

     cd /sys/class/amhdmitx/amhdmitx0

    下面为HDMI OUT 的相关节点状态读取

    1. console:/sys/class/amhdmitx/amhdmitx0 # ls
    2. allm_cap          div40             hdcp_stickmode    power
    3. allm_mode         dv_cap            hdcp_stickstep    preferred_mode
    4. attr              dv_cap2           hdcp_topo_info    rawedid
    5. aud_cap           edid              hdcp_type_policy  ready
    6. aud_ch            edid_parsing      hdcp_ver          rhpd_state
    7. aud_mode          fake_plug         hdmi_config_info  rxsense_policy
    8. avmute            frac_rate_policy  hdmi_hdr_status   rxsense_state
    9. cea_cap           hdcp22_base       hdmi_hsty_config  sink_type
    10. cedst_count       hdcp22_type       hdmi_init         sspll
    11. cedst_policy      hdcp_byp          hdmi_repeater_tx  subsystem
    12. config            hdcp_clkdis       hdmi_used         support_3d
    13. contenttype_cap   hdcp_ctl_lvl      hdmirx_info       swap
    14. contenttype_mode  hdcp_ctrl         hdmitx_drm_flag   sysctrl_enable
    15. dc_cap            hdcp_ksv_info     hdr_cap           uevent
    16. debug             hdcp_lstore       hdr_cap2          valid_mode
    17. dev               hdcp_mode         hdr_mute_frame    vesa_cap
    18. disp_cap          hdcp_pwr          hpd_state         vic
    19. disp_cap_3d       hdcp_repeater     max_exceed        vid_mute
    20. disp_mode         hdcp_rptxlstore   phy               waiting_for_supplier

    cat /sys/class/display/mode   //查看当前输出的状态和分辨率

    cat /sys/class/amhdmitx/amhdmitx0/dc_cap //显示设备支持的色域间及色深

    cat  /sys/class/amhdmitx/amhdmitx0/disp_cap  //显示设备支持的分辨率,*显示当前分辨率

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  • 原文地址：https://blog.csdn.net/BENKG/article/details/126299456