• FPGA——SPI总线控制flash（3）含代码

    前面几篇详细 介绍了SPI的原理，并且实现了对flash芯片的写使能，读状态，擦除，页读，页写

    ​​​​​​FPGA——SPI总线详解（概念）_居安士的博客-CSDN博客_fpga芯片

    FPGA——SPI总线控制flash（1）（含代码）_居安士的博客-CSDN博客

    FPGA——SPI总线控制flash（2）（含代码）_居安士的博客-CSDN博客

    接下来我们需要将各个模块汇合到一起：

    目录

    总线应答模块

    SPI控制模块

    SPI_FLASH总模块 

    总线应答模块

    之前的总线应答都是写在TB文件里面，现在所以模块写齐了之后，需要将多个模块的总线应答汇总在一个模块里，根据请求总线的信号，回复ack。当接收到总线同意通信的信号后，将spi_cs ，spi_clk ，spi_dout ，spi_din传递给总线，传递结束后，请求总线关闭，回复ack。

    总线控制模块需要完成的任务：

    1. 控制5个模块（写使能，读状态，擦除，页写，页读）的总线应答
    2. 根据模块给spi_bus信号（spi_cs ，spi_clk ，spi_dout ，spi_din）
    3. 流程图如下：

     0：给5个模块分配标号

    1：在请求总线开放信号到来时，根据标号给总线应答开放信号

    2：在请求总线关闭信号到来时，采请求总线下降沿，给总线应答关闭信号

    总线一次只能通信一个模块，根据分配的标号，将模块输出的spi_cs ，spi_clk ，spi_dout给总线，总线输出的spi_din给模块

    1. module mux_top(
    2. input clk,
    3. input reset,
    4. //写使能
    5. input mux_wren           ,
    6. output reg  mux_wren_done,
    7. input spi_cs1            ,
    8. input spi_clk1           ,
    9. input spi_dout1          ,
    10. output reg spi_din1      , 
    11. //读状态
    12. input mux_status           ,
    13. output reg  mux_status_done,
    14. input spi_cs2              ,
    15. input spi_clk2             ,
    16. input spi_dout2            ,
    17. output reg spi_din2        , 
    18. //擦除
    19. input mux_earse            ,
    20. output reg  mux_earse_done ,
    21. input spi_cs3              ,
    22. input spi_clk3             ,
    23. input spi_dout3            ,
    24. output reg spi_din3        , 
    25. //页写
    26. input mux_write            ,
    27. output reg  mux_write_done ,
    28. input spi_cs4              ,
    29. input spi_clk4             ,
    30. input spi_dout4            ,
    31. output reg spi_din4        , 
    32. //页读
    33. input mux_read             ,
    34. output reg  mux_read_done  ,
    35. input spi_cs5              ,
    36. input spi_clk5             ,
    37. input spi_dout5            ,
    38. output reg spi_din5        , 
    39. //总线bus
    40. input spi_din  ,
    41. output spi_cs  ,
    42. output spi_clk ,
    43. output spi_dout
    44.  
    45.     );
    46.     
    47.     //输入打一拍
    48.     reg mux_wren_dly  ;
    49.     reg mux_status_dly;
    50.     reg mux_earse_dly ;
    51.     reg mux_write_dly ;
    52.     reg mux_read_dly  ;
    53.     
    54.     always@(posedge clk)begin
    55.      if(reset)begin
    56.       mux_wren_dly   <=1'd0;
    57.         mux_status_dly <=1'd0;
    58.         mux_earse_dly  <=1'd0;
    59.         mux_write_dly  <=1'd0;
    60.         mux_read_dly   <=1'd0;
    61.      end
    62.      else begin
    63.       mux_wren_dly   <=mux_wren  ;
    64.         mux_status_dly <=mux_status;
    65.         mux_earse_dly  <=mux_earse ;
    66.         mux_write_dly  <=mux_write ;
    67.         mux_read_dly   <=mux_read  ;
    68.      end
    69.     end
    70.     
    71.     reg [2:0] mux_mode;//选择写、读、擦除等模式
    72.     reg [1:0] state;//状态机
    73.  
    74. 	always@(posedge clk)begin
    75. 		if(reset)begin
    76. 			mux_mode<=1'd0;
    77. 			state<=2'd0;
    78. 		end
    79. 		else begin
    80. 			mux_wren_done  <=1'd0;
    81.       mux_status_done<=1'd0;
    82.       mux_earse_done <=1'd0;
    83.       mux_write_done <=1'd0;
    84.       mux_read_done  <=1'd0;
    85. 			case(state)
    86. 				2'd0:begin //根据请求总线的信号选择当前模式
    87. 					if(mux_wren_dly)begin
    88. 		        mux_mode<=3'd1;
    89. 		        state<=2'd1;
    90. 		       end
    91. 		       else if(mux_status_dly)begin
    92. 		        mux_mode<=3'd2;
    93. 		        state<=2'd1;
    94. 		       end
    95. 		       else if(mux_earse_dly)begin
    96. 		        mux_mode<=3'd3;
    97. 		        state<=2'd1;
    98. 		       end
    99. 		       else if(mux_write_dly)begin
    100. 		        mux_mode<=3'd4;
    101. 		        state<=2'd1;
    102.            end
    103.            else if(mux_read_dly)begin
    104.             mux_mode<=3'd5;
    105.             state<=2'd1;
    106.            end
    107.            else begin
    108.             mux_mode<=3'd0;
    109.             state<=2'd0;
    110.            end
    111. 				end
    112. 				2'd1:begin//回复同意开启总线
    113. 					case(mux_mode)
    114. 						3'd1:mux_wren_done<=1'd1;
    115. 						3'd2:mux_status_done<=1'd1;
    116. 						3'd3:mux_earse_done<=1'd1;
    117. 						3'd4:mux_write_done<=1'd1;
    118. 						3'd5:mux_read_done<=1'd1;
    119. 					endcase
    120. 					state<=2'd2;
    121. 				end
    122. 				2'd2:begin//回复关闭总线
    123. 					 if(~mux_wren&&mux_wren_dly)begin//在mux_wren下降沿
    124.             mux_wren_done<=1'd1;
    125.             state<=2'd0;
    126.            end
    127.            else if(~mux_status&&mux_status_dly)begin
    128.             mux_status_done<=1'd1;
    129.             state<=2'd0;
    130.            end
    131.            else if(~mux_earse&&mux_earse_dly)begin
    132.             mux_earse_done<=1'd1;
    133.             state<=2'd0;
    134.            end
    135.            else if(~mux_write&&mux_write_dly)begin
    136.             mux_write_done<=1'd1;
    137.             state<=2'd0;
    138.            end
    139.            else if(~mux_read&&mux_read_dly)begin
    140.             mux_read_done<=1'd1;
    141.             state<=2'd0;
    142.            end
    143. 				end
    144. 			endcase
    145. 		end
    146. 	end
    147. 	//总线经过选择之后，发送cs
    148. 	assign spi_cs=(mux_mode==3'd1)?spi_cs1
    149. 								(mux_mode==3'd2)?spi_cs2
    150. 								(mux_mode==3'd3)?spi_cs3
    151. 								(mux_mode==3'd4)?spi_cs4
    152. 								(mux_mode==3'd5)?spi_cs5
    153. 								1'd1;
    154. 	//总线经过选择之后，发送clk						
    155. 	assign spi_clk =(mux_mode==3'd1)? spi_clk1 :
    156.                   (mux_mode==3'd2)? spi_clk2 :
    157.                   (mux_mode==3'd3)? spi_clk3 :
    158.                   (mux_mode==3'd4)? spi_clk4 :
    159.                   (mux_mode==3'd5)? spi_clk5 :
    160.                   1'd0;
    161.   //总线经过选择之后，发送dout               
    162.   assign spi_dout =(mux_mode==3'd1)? spi_dout1 :
    163.                    (mux_mode==3'd2)? spi_dout2 :
    164.                    (mux_mode==3'd3)? spi_dout3 :
    165.                    (mux_mode==3'd4)? spi_dout4 :
    166.                    (mux_mode==3'd5)? spi_dout5 :
    167.                    1'd1;
    168. //把输出的din给模块
    169. always@(*)begin
    170.     if(mux_mode==3'd2)begin
    171.      spi_din2=spi_din;
    172.     end
    173.     else if (mux_mode==3'd5)begin
    174.      spi_din5=spi_din;
    175.     end
    176.     else begin
    177.      spi_din2=1'd1;
    178.      spi_din5=1'd1;
    179.     end
    180.    end
    181.  
    182. endmodule

    SPI控制模块

    spi控制模块需要完成的任务是：

    1 定义操作启动信号，利用操作启动信号来控制每种模块的启动信号

    定义操作信号（0~9），根据操作指令来控制spi里面5个模块（写使能，读状态，擦除，页写，页读）的每种指令

    2 输入想要控制spi里面模块的地址和突发长度

    3 输出写类完成信号（写使能，擦除，页写）和读类完成信号（读状态，页读），

    以及总线忙信号和总线不忙信号

    4 控制写使能模块：输出启动写使能信号，输出写使能指令

    5 控制读状态模块：输出启动读状态信号，输出读状态指令，输入读状态数据

    6 控制擦除模块：输出启动擦除信号，输出擦除指令，输出擦除的地址

    7 控制页写模块：输出页写擦除信号，输出页写指令，输出页写的地址，输出页写的突发长度

    8 控制页读模块：输出页读擦除信号，输出页读指令，输出页读的地址，输出页读的突发长度，输入页读的数据

     编写代码如下：

    1. module spi_control(
    2. input clk,
    3. input reset,
    4. //操作信号
    5. input       op_en          ,//启动操作
    6. input [3:0] op_cmd         ,//0:写使能04h 1：写使能06h 2：读状态05h 3：读状态35h 4：擦除20h 5：擦除52h 6：擦除D8h 7：擦除整片 8：页写 9：页读
    7. input [23:0]op_addr        ,
    8. input [8:0] op_brust_length,
    9. output reg  wr_cmd_done    , //返回写类done：写使能，页写，擦除
    10. output reg  rd_cmd_done    ,//返回读类done：读状态寄存器，页读
    11. output reg  rd_cmd_fail    ,//读状态寄存器为忙
    12. output reg  status_ok      ,
    13.  
    14. //写使能
    15. output reg start_wr        ,
    16. output reg wren_cmd        ,
    17. input      wren_done       ,
    18. //读状态
    19. output reg start_status    ,
    20. output reg status_cmd      ,
    21. input[7:0] status_data     ,
    22. input      status_done     ,
    23. //擦除
    24. output reg       start_erase ,
    25. output reg [1:0] erase_cmd   , 
    26. output reg [23:0]erase_addr  ,
    27. input            erase_done  ,
    28. //页写
    29. output reg       start_write      ,
    30. output reg [8:0] wr_brust_length     ,
    31. output reg [23:0]write_addr       ,
    32. input            write_done       ,
    33. //页读
    34. output reg       start_read      ,
    35. output reg [8:0] rd_brust_length    ,
    36. output reg [23:0]read_addr       ,
    37. input            read_done       
    38.  
    39.     );
    40.     
    41.   //输出start信号和对应的命令
    42.     
    43.     always@(posedge clk)begin
    44.     	if(reset)begin
    45.     		wr_cmd_done <=1'd0;
    46.         rd_cmd_done <=1'd0;
    47.         rd_cmd_fail <=1'd0;
    48.         status_ok   <=1'd0;
    49. 				start_wr       <=1'd0;
    50.         wren_cmd       <=1'd0;
    51.         start_status   <=1'd0;
    52.         status_cmd     <=1'd0;
    53.         start_erase    <=1'd0;
    54.         erase_cmd      <=2'd0;
    55.         erase_addr     <=24'd0;
    56.         start_write    <=1'd0;
    57.         wr_brust_length<=8'd0;
    58.         write_addr     <=24'd0;
    59.         start_read     <=1'd0;
    60.         rd_brust_length<=8'd0;
    61.         read_addr      <=24'd0;
    62.  
    63.     	end
    64.     	else begin
    65.     				if(op_en)begin
    66.     					case(op_cmd)
    67.     						4'd0:begin//写使能04h
    68.                  start_wr<=1'd1;
    69.                  wren_cmd<=1'd0;
    70.                 end
    71.                 4'd1:begin//写使能06h
    72.                  start_wr<=1'd1;
    73.                  wren_cmd<=1'd1;
    74.                 end
    75.                 4'd2:begin//读状态05h
    76.                  start_status<=1'd1;
    77.                  status_cmd<=1'd0;
    78.                 end
    79.                 4'd3:begin//读状态35h
    80.                  start_status<=1'd1;
    81.                  status_cmd<=1'd1;
    82.                 end
    83.                 4'd4:begin//擦除20h
    84.                  start_erase<=1'd1;
    85.              	    erase_cmd<=2'd0;
    86.              	    erase_addr  <=op_addr;
    87.              	   end
    88.              	   4'd5:begin//擦除52h
    89.              	    start_erase<=1'd1;
    90.              	    erase_cmd<=2'd1;
    91.              	    erase_addr  <=op_addr;
    92.              	   end
    93.              	   4'd6:begin//擦除D8h
    94.              	    start_erase<=1'd1;
    95.              	    erase_cmd<=2'd2;
    96.              	    erase_addr  <=op_addr;
    97.              	   end
    98.              	   4'd7:begin//擦除整片
    99.              	    start_erase<=1'd1;
    100.              	    erase_cmd<=2'd3;
    101.              	    erase_addr  <=op_addr;
    102.              	   end
    103.              	   4'd8:begin//页写
    104.              	    start_write<=1'd1;
    105.              	    wr_brust_length<=op_brust_length;
    106.              	    write_addr  <=op_addr;
    107.              	   end
    108.              	   4'd9:begin//页读
    109.              	    start_read<=1'd1;
    110.              	    rd_brust_length<=op_brust_length;
    111.              	    read_addr  <=op_addr;
    112.              	   end
    113.     					endcase
    114.     				end
    115.     				else begin
    116.     					start_wr<=1'd0;
    117.               start_status<=1'd0;
    118.               start_erase<=1'd0;
    119.               start_write<=1'd0;
    120.               start_read<=1'd0;
    121.     				end
    122.     			
    123.     	end
    124.     end
    125.     
    126.       always@(posedge clk)begin//输出写类完成信号
    127.        if(wren_done||erase_done||write_done)begin
    128.         wr_cmd_done<=1'b1;
    129.        end
    130.        else begin
    131.         wr_cmd_done<=1'b0;
    132.        end
    133.       end
    134.       
    135.       always@(posedge clk)begin//输出读类完成信号
    136.        if(status_done||read_done)begin
    137.         rd_cmd_done<=1'b1;
    138.        end
    139.        else begin
    140.         rd_cmd_done<=1'b0;
    141.        end
    142.       end
    143.  
    144.  
    145.  
    146. always@(posedge clk)begin
    147. 	if((status_data[0]==1'b0)&&status_done)begin//读状态总线不忙
    148. 		status_ok<=1'b1;
    149. 	end
    150. 	else begin
    151. 		status_ok<=1'b0;
    152. 	end
    153. end
    154.  
    155. always@(posedge clk)begin
    156.  if((status_data[0]==1) &&status_done)begin//status_data_dly=1表示状态忙
    157.   rd_cmd_fail<=1'b1;
    158.  end
    159.  else begin
    160.   rd_cmd_fail<=1'b0;
    161.  end
    162. end
    163.  
    164.  
    165. endmodule

    SPI_FLASH总模块 

    接下来把所有的模块例化到一起;

    1. module spi_flash(
    2. input clk,
    3. input reset  ,
    4. input clk_wr ,
    5. input clk_rd ,
    6. //控制信号
    7. input        op_en          ,
    8. input [3:0]  op_cmd         ,
    9. input [23:0] op_addr        ,
    10. input [8:0]  op_brust_length,
    12. //done信号
    13. output wr_cmd_done,
    14. output rd_cmd_done,
    15. output rd_cmd_fail,
    16. //bus
    17. output spi_cs  ,
    18. output spi_clk ,
    19. output spi_dout,
    20. input  spi_din 
    21.     );
    22. // 写使能
    23. wire  start_wr         ;
    24. // 读状态                  
    25. wire start_status      ;
    26. //擦                    
    27. wire start_erase       ;
    28. wire erase_cmd_out     ;
    29. //写               
    30. wire start_write       ;
    31. wire din               ;
    32. //计时器                  
    33. wire time_done         ;
    34. wire write_en          ;
    35. wire erase_en          ;
    36. wire erase_cmd         ;
    37. //spi控制                     
    38. wire wren_cmd          ;
    39. wire wren_done         ;
    40.  
    41. wire status_cmd        ;
    42. wire status_data       ;
    43. wire status_done       ;
    44.  
    45. wire erase_addr        ;
    46. wire erase_done        ;
    47.  
    48. wire write_addr        ;
    49. wire write_done        ;
    50.  
    51. wire read_addr         ;
    52. wire read_done         ;
    53. //总线模式选择
    54. wire mux_wren          ;
    55. wire mux_wren_done     ;
    56. wire spi_cs1           ;
    57. wire spi_clk1          ;
    58. wire spi_dout1         ;
    59. wire spi_din1          ;
    60.                        
    61. wire mux_status        ;
    62. wire mux_status_done   ;
    63. wire spi_cs2           ;
    64. wire spi_clk2          ;
    65. wire spi_dout2         ;
    66. wire spi_din2          ;
    67.                        
    68. wire mux_earse         ;
    69. wire mux_earse_done    ;
    70. wire spi_cs3           ;
    71. wire spi_clk3          ;
    72. wire spi_dout3         ;
    73. wire spi_din3          ;
    74.                        
    75. wire mux_write         ;
    76. wire mux_write_done    ;
    77. wire spi_cs4           ;
    78. wire spi_clk4          ;
    79. wire spi_dout4         ;
    80. wire spi_din4          ;
    81.                        
    82. wire mux_read          ;
    83. wire mux_read_done     ;
    84. wire spi_cs5           ;
    85. wire spi_clk5          ;
    86. wire spi_dout5         ;
    87. wire spi_din5          ;
    88.  
    89.      
    90.     
    91.     
    92.     
    93.     //-------------------------------------------写使能
    94.     wr_enable inst_wr_enable(
    95.     .clk       (clk),
    96.    .reset         (reset)           ,
    97.    .start_wr      (start_wr)        ,//开始写使能
    98.    .wren_cmd      (wren_cmd)        ,//指令（0/1）
    99.    .mux_wren_done (mux_wren_done)   ,//总线返回
    100.    .wren_done     (wren_done)       ,//写使能完成
    101.    .mux_wren      (mux_wren)        ,//请求总线
    102.    .spi_cs        (spi_cs1)          ,//总线发送的片选线
    103.    .spi_clk       (spi_clk1)         ,//总线发送的clk线
    104.    .spi_dout      (spi_dout1)         //总线发送的DI线
    105.     );
    106.     //----------------------------------------读状态
    107.     read_status inst_read_status(
    108.        .clk       (clk),
    109.        .reset          (reset)       ,
    110.        .start_status   (start_status)       ,//开始读状态
    111.        .status_cmd     (status_cmd)       ,//读状态指令
    112.        .mux_status_done(mux_status_done)       ,//总线返回
    113.        .spi_din        (spi_din2)       ,//由总线输入
    114.        .mux_status     (mux_status)  ,//请求总线
    115.        .status_done    (status_done)  ,//读状态完成
    116.        .status_data    (status_data)  ,//读状态返回8位数据
    117.        .spi_cs         (spi_cs2)  ,//片选信号
    118.        .spi_clk        (spi_clk2)  ,//时钟信号
    119.        .spi_dout       (spi_dout2)   //总线输入
    120.     );
    121.     //--------------------------------------------------擦除
    122.     erase_top  erase_top(
    123.         .clk       (clk) ,
    124.         .reset          (reset) ,
    125.         .start_erase    (start_erase) ,
    126.         .erase_cmd      (erase_cmd) ,//擦除指令
    127.         .erase_addr     (erase_addr) ,//擦除地址
    128.         .mux_erase_done (mux_erase_done) ,
    129.         .time_done      (time_done) ,//计时完成
    130.                         
    131.         .mux_erase      (mux_erase) ,
    132.         .spi_cs         (spi_cs3) ,
    133.         .spi_clk        (spi_clk3) ,
    134.         .spi_dout       (spi_dout3) ,
    135.         .erase_done     (erase_done) ,
    136.         .erase_en     (erase_en)
    137.     );
    138.     //-----------------------------------------------------页写
    139.      write_top inst_write_top(
    140.        .clk       (clk),    
    141.        .reset       (reset)     ,
    142.        .start_write (start_write)     ,//启动页写
    143.       //fifo部分驱动接口
    144.        .brust_length  (brust_length)   ,//突发长度
    145.        .write_addr    (write_addr)     ,//初始地址
    146.        .clk_wr        (clk_wr)         ,//fifo时钟
    147.        .wr_fifo_en    (wr_fifo_en)     ,//fifo写使能
    148.        .din           (wr_fifo_data)   ,//写数据
    149.        .wr_fifo_empty (wr_fifo_empty)  ,//fifo空
    150.        .wr_fifo_full  (wr_fifo_full)   ,//fifo满
    151.       //总线接口
    152.        .spi_cs          (spi_cs4)  ,//spi片选
    153.        .spi_clk         (spi_clk4)  ,//spi时钟
    154.        .spi_dout        (spi_dout4)  ,//spi输出
    155.        .mux_write       (mux_write)  ,//请求总线
    156.        .mux_write_done  (mux_write_done)  ,//总线应答
    157.        .write_done      (write_done)  ,//页写完成
    158.       //计时器
    159.        .time_done (time_done)       ,//计时完成
    160.        .write_en  (write_en)  //启动计时
    161.     );
    162.     //-------------------------------------------页读
    163.      read_top inst_read_top(
    164.        .clk       (clk),        
    165.        .reset         (reset)         ,
    166.        .rd_clk        (rd_clk)         ,
    167.        .start_read    (start_read)         ,//开始页读
    168.        .read_addr     (read_addr)         , //页读地址
    169.        .brust_length  (brust_length)         ,//突发长度
    170.        .rd_fifo_en    (rd_fifo_en)         ,//fifo读使能
    171.        .rd_fifo_data  (rd_fifo_data)         ,//从fifo读出的数据
    172.        .rd_fifo_empty (rd_fifo_empty)         ,
    173.        .rd_fifo_full  (rd_fifo_full)         ,
    174.        .spi_cs        (spi_cs5)           ,
    175.        .spi_clk       (spi_clk5)           ,
    176.        .spi_dout      (spi_dout5)           ,
    177.        .spi_din       (spi_din5)           ,
    178.        .mux_read      (mux_read)           ,
    179.        .mux_read_done (mux_read_done)           ,
    180.        .read_done     (read_done)
    181.     );
    182.     //-------------------------------------------time_top模块
    183.     erase_time inst_erase_time(
    184.       .clk       (clk),
    185.       .reset     (reset),
    186.       .write_en  (write_en),//页写计时
    187.       .erase_en  (erase_en),//擦除计时
    188.       .erase_cmd (erase_cmd),//擦除模式选择
    189.       .time_done (time_done)
    190.     );
    191.     //------------------------------------------spi_control模块
    192.     spi_control inst_spi_control(
    193.       .clk            (clk),
    194.       .reset          (reset),
    195. //操作信号            
    196.       .op_en          (op_en),
    197.       .op_cmd         (op_cmd),//0:写使能04h 1：写使能06h 2：读状态05h 3：读状态35h 4：擦除20h 5：擦除52h 6：擦除D8h 7：擦除整片 8：页写 9：页读
    198.       .op_addr        (op_addr),
    199.       .op_brust_length(op_brust_length),
    200.       .wr_cmd_done    (wr_cmd_done), //返回写类done：写使能，页写，擦除
    201.       .rd_cmd_done    (rd_cmd_done),//返回读类done：读状态寄存器，页读
    202.       .rd_cmd_fail    (rd_cmd_fail),//读状态寄存器为忙
    203. //写使能              
    204.       .start_wr       (start_wr) ,
    205.       .wren_cmd       (wren_cmd) ,
    206.       .wren_done      (wren_done) ,
    207. //读状态             
    208.       .start_status   (start_status) ,
    209.       .status_cmd     (status_cmd) ,
    210.       .status_data    (status_data) ,
    211.       .status_done    (status_done) ,
    212. //擦除                
    213.       .start_erase    (start_erase) ,
    214.       .erase_cmd      (erase_cmd) , 
    215.       .erase_addr     (erase_addr) ,
    216.       .erase_done     (erase_done) ,
    217. //页写                
    218.       .start_write    (start_write)  ,
    219.       .wr_brust_length   (wr_brust_length)  ,
    220.       .write_addr     (write_addr)  ,
    221.       .write_done     (write_done)  ,
    222. //页读               
    223.       .start_read     (start_read) ,
    224.       .rd_brust_length(rd_brust_length) ,
    225.       .read_addr      (read_addr) ,
    226.       .read_done      (read_done) 
    227.     );
    228.     //-------------------------------------------总线交互模块
    229.      mux_top mux_top(
    230.      .clk              (clk)  ,
    231.      .reset            (reset)  ,
    232. //写使能               
    233.       .mux_wren         (mux_wren)  ,
    234.       .mux_wren_done    (mux_wren_done)  ,
    235.       .spi_cs1          (spi_cs1)  ,
    236.       .spi_clk1         (spi_clk1)  ,
    237.       .spi_dout1        (spi_dout1)  ,
    238.       .spi_din1         (spi_din1 )  , 
    239. //读状态               
    240.       .mux_status      (mux_status)     ,
    241.       .mux_status_done (mux_status_done)     ,
    242.       .spi_cs2         (spi_cs2)     ,
    243.       .spi_clk2        (spi_clk2)     ,
    244.       .spi_dout2       (spi_dout2)     ,
    245.       .spi_din2        (spi_din2)     , 
    246. //擦除                 
    247.       .mux_earse       (mux_earse)     ,
    248.       .mux_earse_done  (mux_earse_done)     ,
    249.       .spi_cs3         (spi_cs3)     ,
    250.       .spi_clk3        (spi_clk3)     ,
    251.       .spi_dout3       (spi_dout3)     ,
    252.       .spi_din3        (spi_din3)     , 
    253. //页写                 
    254.        .mux_write      (mux_write)      ,
    255.        .mux_write_done (mux_write_done)      ,
    256.        .spi_cs4        (spi_cs4)      ,
    257.        .spi_clk4       (spi_clk4)      ,
    258.        .spi_dout4      (spi_dout4)      ,
    259.        .spi_din4       (spi_din4)      , 
    260. //页读                 
    261.        .mux_read       (mux_read)      ,
    262.        .mux_read_done  (mux_read_done)      ,
    263.        .spi_cs5        (spi_cs5)      ,
    264.        .spi_clk5       (spi_clk5)      ,
    265.        .spi_dout5      (spi_dout5)      ,
    266.        .spi_din5       (spi_din5)      , 
    267. //总线bus              
    268.        .spi_din        (spi_din)    ,
    269.        .spi_cs         (spi_cs)    ,
    270.        .spi_clk        (spi_clk)    ,
    271.        .spi_dout       (spi_dout)
    272.     );
    273. endmodule

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  • 原文地址：https://blog.csdn.net/weixin_46188211/article/details/125947775