• Zynq-Linux移植学习笔记之66- 国产ZYNQ通过裕太PHY8521连接国产交换芯片

    1、背景介绍

    ZYNQ通过裕太PHY 8521主要连接两种国产交换芯片，一种为盛科的CTC8096，另一种为32所的JEM5396。框图示意如下：

    2、硬件状态确认

    首先检查phy的模式，确认为SGMII_MAC-RGMII_PHY

    可通过读出A001寄存器确认状态

    读出来应该是0x8155

    这样确保状态对

    3、PHY软件配置

    PHY软件需要配置为强制千兆

    ./phyreg.elf eth1 0x0 0x340

    设置phy的tx_delay

    一般设置a003寄存器为0xf8或者0xfa

    Phyreg代码如下

    1. /*
    2.  ============================================================================
    3.  Name        : main.c
    4.  Author      : 123
    5.  Version     :
    6.  Copyright   : Your copyright notice
    7.  Description : Hello World in C
    8.  ============================================================================
    9.  */
    10.  
    11. #include 
    12. #include 
    13. #include 
    14. #include 
    15. #include 
    16. #include 
    17. #include 
    18. #include 
    19. #include 
    20. #include 
    21. #include 
    22.  
    23. #define reteck(ret) \
    24. 	if(ret < 0){ \
    25. 		printf("%m! \"%s\" : line: %d\n", __func__, __LINE__); \
    26. 		goto lab; \
    27. }
    28. #define help() \
    29. 	printf("mdio:\n"); \
    30. 	printf("read operation: mdio reg_addr\n"); \
    31. 	printf("write operation: mdio reg_addr value\n"); \
    32. 	printf("For example:\n"); \
    33. 	printf("mdio eth0 1\n"); \
    34. 	printf("mdio eth0 0 0x12\n\n"); \
    35. 	exit(0);
    36.  
    37. int sockfd;
    38.  
    39. int main(int argc, char *argv[]) {
    40. 	if (argc == 1 || !strcmp(argv[1], "-h")) {
    41. 		help()
    42. 		;
    43. 	}
    44. 	struct mii_ioctl_data *mii = NULL;
    45. 	struct ifreq ifr;
    46. 	int ret;
    47. 	memset(&ifr, 0, sizeof(ifr));
    48. 	strncpy(ifr.ifr_name, argv[1], IFNAMSIZ - 1);
    49. 	sockfd = socket(PF_LOCAL, SOCK_DGRAM, 0);
    50. 	reteck(sockfd);
    51. //get phy address in smi bus
    52. 	ret = ioctl(sockfd, SIOCGMIIPHY, &ifr);
    53. 	reteck(ret);
    54. 	mii = (struct mii_ioctl_data*) &ifr.ifr_data;
    55. 	if (argc == 3) {
    56. 		mii->reg_num = (uint16_t) strtoul(argv[2], NULL, 0);
    57. 		ret = ioctl(sockfd, SIOCGMIIREG, &ifr);
    58. 		reteck(ret);
    59. 		printf("read phy addr: 0x%x reg: 0x%x value : 0x%x\n", mii->phy_id,
    60. 				mii->reg_num, mii->val_out);
    61. 	} else if (argc == 4) {
    62. 		mii->reg_num = (uint16_t) strtoul(argv[2], NULL, 0);
    63. 		mii->val_in = (uint16_t) strtoul(argv[3], NULL, 0);
    64. 		ret = ioctl(sockfd, SIOCSMIIREG, &ifr);
    65. 		reteck(ret);
    66. 		printf("write phy addr: 0x%x reg: 0x%x value : 0x%x\n", mii->phy_id,
    67. 				mii->reg_num, mii->val_in);
    68. 	}
    69. 	lab: close(sockfd);
    70. 	return 0;
    71. }

    4、交换芯片端配置

    交换芯片端与PHY相连的端口需要配置强制千兆模式

    针对CTC8096（一般在SDK应用内配置）

    ctc8096端将对应端口强制千兆

    1. port 0x0007 auto-neg disable
    2.  
    3. port 0x0007 property auto-neg-mode sgmii-slaver

    针对JEM5396（一般在UBOOT阶段配置）

    1. printf("Set Port 5 CONNECT TO ZYNQ SPEED 1000M\n");
    2.  
    3. workBuf[0] = 0x8b;
    4.  
    5. workBuf[1] = 0x0;
    6.  
    7. writeBCM5396_2(&spi, 0, 0x65, workBuf);  
    8.  
    9.  
    10.  
    11.  
    12.  
    13. workBuf[0] = 0x40;
    14.  
    15. workBuf[1] = 0x1;  
    16.  
    17. Status = writeBCM5396(&spi, 0x15, 0x0, workBuf );  

    JEM5396配置的详细代码如下：

    1. // SPDX-License-Identifier: GPL-2.0+
    2. /*
    3.  * (C) Copyright 2001-2015
    4.  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
    5.  * Joe Hershberger, National Instruments
    6.  */
    7.  
    8. #include 
    9. #include 
    10. #include 
    11. #include 
    12. #include 
    13. #include 
    14.  
    15. #define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
    16. 		(*(volatile u32 * )((BaseAddr) + (RegOffset)))
    17.  
    18.  
    19. #define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
    20. 		*(volatile u32 *) ((BaseAddr) + RegOffset) = Data
    21.  
    22.  
    23. #define AD9520READ	(0x80)
    24. #define AD9520WRITE	(0x00)
    25.  
    26. /*-----------------------国产ZYNQ GPIO  通用代码--------------------------------------------*/
    27. #define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
    28. #define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
    29. #define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
    30. #define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
    31. #define XGPIOPS_DIRM_OFFSET	 0x00000004U  //0x00000204U  /* Direction Mode Register, RW */
    32. #define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
    33. #define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
    34. #define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
    35. #define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
    36. #define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
    37. #define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
    38. #define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
    39. #define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
    40.  
    41.  
    42. #define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
    43. #define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
    44. #define XGPIOPS_REG_MASK_OFFSET  0x00000100U  /* Registers offset */ //0x00000040U 
    45.  
    46.  
    47. /* For backwards compatibility */
    48. #define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
    49.  
    50. #define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU
    51. #define XGPIOPS_INTTYPE_BANK1_RESET  0x3FFFFFFFU
    52. #define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
    53. #define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU
    54.  
    55. #define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
    56. #define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
    57. #define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
    58. #define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
    59. #define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
    60. /*@}*/
    61.  
    62. #define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
    63. #define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
    64. #define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
    65. #define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
    66.  
    67. #define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a GPIO device */
    68. #define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
    69.  
    70. #define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /*< Max pins in the GPIO device*/
    71.  
    72. #define LED_DELAY 	10000000
    73. #define FLASH_RESET_GPIO 0x41220000
    74. #define FLASH_RST_PERIOD 600000
    75.  
    76. #define FIFO_CFG_GPIO 0x41210000
    77. #define FIFO_DONE_GPIO 0x41220000
    78.  
    79. #define UBOOT_CFG_GPIO 0x41250000
    80.  
    81. #define GGF_REST_GPIO 0x41260000
    82. #define DBFGKJ_REST_GPIO 0x412A0000
    83. #define FIRST_V_GPIO 0x41260000
    84. #define SECOND_V_GPIO 0x41270000
    85. #define THIRD_V_GPIO 0x41280000
    86. #define FORTH_V_GPIO 0x41290000
    87.  
    88.  
    89. typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
    90.  
    91.  
    92. typedef struct {
    93. 	u16 DeviceId;		/**< Unique ID of device */
    94. 	u32 BaseAddr;		/**< Register base address */
    95. } XGpioPs_Config;
    96.  
    97.  
    98. typedef struct {
    99. 	XGpioPs_Config GpioConfig;	/**< Device configuration */
    100. 	u32 IsReady;			/**< Device is initialized and ready */
    101. 	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
    102. 	void *CallBackRef; 		/**< Callback ref for bank handlers */
    103. } XGpioPs;
    104.  
    105.  
    106. XGpioPs_Config XGpioPs_ConfigTable[] =
    107. {
    108. 	{
    109. 		0,
    110. 		0xE0003000
    111. 	}
    112. };
    113.  
    114. XGpioPs_Config *g_GpioConfig;
    115.  
    116. void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
    117. {
    118. 	/*
    119. 	 * This structure defines the mapping of the pin numbers to the banks when
    120. 	 * the driver APIs are used for working on the individual pins.
    121. 	 */
    122. 	u32 XGpioPsPinTable[] = {
    123. 		(u32)31, /* 0 - 31, Bank 0 */
    124. 		(u32)63, /* 32 - 53, Bank 1 */
    125. 		(u32)95, /* 54 - 85, Bank 2 */
    126. 		(u32)127 /* 86 - 117 Bank 3 */
    127. 	};
    128. 	*BankNumber = 0U;
    129. 	while (*BankNumber < 4U) {
    130. 		if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
    131. 			break;
    132. 		}
    133. 		(*BankNumber)++;
    134.     }
    135. 	if (*BankNumber == (u8)0) {
    136. 		*PinNumberInBank = PinNumber;
    137. 	} else {
    138. 		*PinNumberInBank = (u8)((u32)PinNumber %
    139. 					(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
    140. 	}
    141. }
    142.  
    143.  
    144. void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
    145. {
    146. 	u8 Bank;
    147. 	u8 PinNumber;
    148. 	u32 DirModeReg;
    149.  
    150. 	/*
    151. 	 * Get the Bank number and Pin number within the bank.
    152. 	 */
    153. 	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
    154.  
    155. 	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
    156. 				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
    157. 				      XGPIOPS_DIRM_OFFSET);
    158.  
    159. //	DirModeReg = XGpioPs_ReadReg(0xE000A244,0);
    160.  
    161.  
    162. 	if (Direction!=(u32)0) { /*  input Direction */
    163. 		DirModeReg |= ((u32)1 << (u32)PinNumber);
    164. 	} else { /* output Direction */
    165. 		DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
    166. 	}
    167.  
    168.  
    169. 	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
    170. 			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
    171. 			 XGPIOPS_DIRM_OFFSET, DirModeReg);
    172.  
    173. //	XGpioPs_WriteReg(0xE000A244, 0,DirModeReg);
    174. }
    175.  
    176.  
    177. void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
    178. {
    179. 	u8 Bank;
    180. 	u8 PinNumber;
    181. 	u32 OpEnableReg;
    182.  
    183. 	/*
    184. 	 * Get the Bank number and Pin number within the bank.
    185. 	 */
    186. 	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
    187.  
    188.  
    189. 	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
    190. 				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
    191. 				       XGPIOPS_OUTEN_OFFSET);
    192.  
    193. //	OpEnableReg = XGpioPs_ReadReg(0xE000A248,0);
    194.  
    195.  
    196. 	if (OpEnable != (u32)0) { /*  Enable Output Enable */
    197. 		OpEnableReg |= ((u32)1 << (u32)PinNumber);
    198. 	} else { /* Disable Output Enable */
    199. 		OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
    200. 	}
    201. 	
    202.  
    203. 	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
    204. 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
    205. 			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
    206. //	XGpioPs_WriteReg(0xE000A248,0, OpEnableReg);
    207. }
    208.  
    209.  
    210. void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
    211. {
    212. 	u32 Value;
    213. 	u8 Bank;
    214. 	u8 PinNumber;
    215. 	u32 DataVar = Data;
    216.  
    217. 	/*
    218. 	 * Get the Bank number and Pin number within the bank.
    219. 	 */
    220. 	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
    221. //
    222. //	if (PinNumber > 15U) {
    223. 		/*
    224. 		 * There are only 16 data bits in bit maskable register.
    225. 		 */
    226. //		PinNumber -= (u8)16;
    227. //		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
    228. //	} else {
    229. //		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
    230. //	}
    231.  
    232. 	/*
    233. 	 * Get the 32 bit value to be written to the Mask/Data register where
    234. 	 * the upper 16 bits is the mask and lower 16 bits is the data.
    235. 	 */
    236. 	DataVar &= (u32)0x01;
    237. 	Value = ((DataVar << PinNumber) | 0x00000000U);
    238.  
    239. 	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
    240. 			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
    241. 			  XGPIOPS_DATA_LSW_OFFSET, Value);
    242. }
    243.  
    244. u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
    245. {
    246. 	u8 Bank;
    247. 	u8 PinNumber;
    248.  
    249. 	/*
    250. 	 * Get the Bank number and Pin number within the bank.
    251. 	 */
    252. 	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
    253.  
    254. 	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
    255. 				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
    256. 				 XGPIOPS_DATA_LSW_OFFSET) >> (u32)PinNumber) & (u32)1;
    257.  
    258. }
    259.  
    260.  
    261. void mygpio_init(int mioPinNum)
    262. {
    263. 	XGpioPs Gpio;
    264. 	g_GpioConfig = &XGpioPs_ConfigTable[0];
    265.  
    266. 	//Initialize the GPIO device.
    267.  
    268. 	Gpio.IsReady = 0U;
    269. 	Gpio.GpioConfig.BaseAddr = g_GpioConfig->BaseAddr;
    270.  
    271. 	Gpio.GpioConfig.DeviceId = 0;
    272.  
    273. 	/*
    274. 	 * Indicate the component is now ready to use.
    275. 	 */
    276. 	Gpio.IsReady = 0x11111111U;
    277.  
    278. 	//Initialize the GPIO device. end
    279. 	XGpioPs_SetDirectionPin(&Gpio, mioPinNum, 1);
    280.  
    281. 	// MIO0
    282. 	XGpioPs_WritePin(&Gpio, mioPinNum, 0x1);
    283. 	if(XGpioPs_ReadPin(&Gpio,mioPinNum) != 1)
    284. 	printf("mio reset phy failed \n\r");
    285. 	udelay(2000);
    286.  
    287. 	XGpioPs_WritePin(&Gpio, mioPinNum, 0x0);
    288. 	if(XGpioPs_ReadPin(&Gpio,mioPinNum) != 0)
    289. 	printf("mio reset phy failed \n\r");
    290. 	udelay(2000);
    291.  
    292. 	XGpioPs_WritePin(&Gpio, mioPinNum, 0x1);
    293. 	if(XGpioPs_ReadPin(&Gpio,mioPinNum) != 1)
    294. 	printf("mio reset phy failed \n\r");
    295.  
    296. }
    297.  
    298.  
    299. //
    300. /*   		              JEM5396 读写通用代码                              */
    301. //
    302. #ifndef TRUE
    303. #define TRUE		1U
    304. #endif
    305.  
    306. #ifndef FALSE
    307. #define FALSE		0U
    308. #endif
    309.  
    310. #ifndef NULL
    311. #define NULL		0U
    312. #endif
    313.  
    314. #ifndef FPAR_SPIPS_0_DEVICE_ID
    315.     #define FPS_SPI0_DEVICE_ID          (0)
    316. #else
    317.     #define FPS_SPI0_DEVICE_ID          FPAR_SPIPS_0_DEVICE_ID
    318. #endif
    319.  
    320. #ifndef  FPS_SPI0_BASEADDR
    321.     #define FPS_SPI0_BASEADDR           (0xe0001000)
    322. #endif
    323.  
    324. #ifndef FPAR_SPIPS_1_DEVICE_ID
    325.     #define FPS_SPI1_DEVICE_ID          (1)
    326. #else
    327.     #define FPS_SPI1_DEVICE_ID          FPAR_SPIPS_1_DEVICE_ID
    328. #endif
    329.  
    330. #ifndef  FPS_SPI1_BASEADDR
    331.     #define FPS_SPI1_BASEADDR           (0xe0021000)
    332. #endif
    333.  
    334.  
    335. #define SLCR_SPI0_CTRL       		(0x300)
    336. #define SLCR_SPI1_CTRL       		(0x300)
    337. #define SPI0_APB_RST         		(0x0)
    338. #define SPI1_APB_RST         		(0x1)
    339. #define SPI0_REF_RST         		(0x2)
    340. #define SPI1_REF_RST        		(0x3)
    341. #define SLCR_LOCK            		(0x004)
    342. #define SLCR_UNLOCK         		(0x008)
    343. #define FPS_SLCR_BASEADDR            	(0xE0026000)
    344.  
    345. register
    346. #define SPIPS_MSTR_OFFSET           (0x100)
    347. #define SPIPS_CTRLR0_OFFSET         (0x00)
    348. #define SPIPS_CTRLR1_OFFSET         (0x04)
    349. #define SPIPS_SSIENR_OFFSET         (0x08)
    350. #define SPIPS_MVCR_OFFSET           (0x0C)
    351. #define SPIPS_SER_OFFSET            (0x10)
    352. #define SPIPS_BAUDR_OFFSET          (0x14)
    353. #define SPIPS_TXFTLR_OFFSET         (0x18)
    354. #define SPIPS_RXFTLR_OFFSET         (0x1C)
    355. #define SPIPS_TXFLR_OFFSET          (0x20)
    356. #define SPIPS_RXFLR_OFFSET          (0x24)
    357. #define SPIPS_SR_OFFSET             (0x28)
    358. #define SPIPS_IMR_OFFSET            (0x2C)
    359. #define SPIPS_ISR_OFFSET            (0x30)
    360. #define SPIPS_RISR_OFFSET           (0x34)
    361. #define SPIPS_TXOICR_OFFSET         (0x38)
    362. #define SPIPS_RXOICR_OFFSET         (0x3C)
    363. #define SPIPS_RXUICR_OFFSET         (0x40)
    364. #define SPIPS_MSTICR_OFFSET         (0x44)
    365. #define SPIPS_ICR_OFFSET            (0x48)
    366. #define SPIPS_DMACR_OFFSET          (0x4C)
    367. #define SPIPS_DMATDLR_OFFSET        (0x50)
    368. #define SPIPS_DMARDLR_OFFSET        (0x54)
    369. #define SPIPS_IDR_OFFSET            (0x58)
    370. #define SPIPS_VERSION_OFFSET        (0x5C)
    371. #define SPIPS_DR_OFFSET             (0x60)
    372. #define SPIPS_RX_SAMPLE_OFFSET      (0xf0)
    373. #define SPIPS_SCTRLR0_OFFSET        (0xf4)
    374. #define SPIPS_RSVD1_OFFSET          (0xf8)
    375. #define SPIPS_RSVD2_OFFSET          (0xfc)
    376.  
    377. #define FMSH_ReadReg(baseAddr, offSet)		*((volatile unsigned int *)(baseAddr + offSet))
    378. #define FMSH_WriteReg(baseAddr, offSet, data)	*((volatile unsigned int *)(baseAddr + offSet)) = data
    379.  
    380.  
    381. typedef struct {
    382.     u16 deviceId;		            /**< Unique ID of device */
    383.     u32 baseAddress;                /**< APB Base address of the device */
    384. } FSpiPs_Config_T;
    385.  
    386. #define FPS_SPI_NUM_INSTANCES       (1)
    387.  
    388. FSpiPs_Config_T FSpiPs_ConfigTable[] =
    389. {
    390. 	{
    391. 		FPS_SPI0_DEVICE_ID,
    392. 		FPS_SPI0_BASEADDR
    393. 	},
    394. 	{
    395. 		FPS_SPI1_DEVICE_ID,
    396. 		FPS_SPI1_BASEADDR
    397. 	}
    398. };
    399. FSpiPs_Config_T* FSpiPs_LookupConfig(u16 deviceId)
    400. {
    401.     int index;
    402.     FSpiPs_Config_T* cfgPtr = NULL;
    403.  
    404.     for (index = 0; index < FPS_SPI_NUM_INSTANCES; index++) {
    405.         if (FSpiPs_ConfigTable[index].deviceId == deviceId) {
    406.             cfgPtr = &FSpiPs_ConfigTable[index];
    407.             break;
    408.         }
    409.     }
    410.     return cfgPtr;
    411. }
    412.  
    413. typedef unsigned char BOOL;
    414.  
    415. typedef void (*FSpiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
    416.                                       u32 ByteCount);
    417.  
    418. typedef struct FSpiPs_Tag{
    419.     FSpiPs_Config_T config;         /**< Configuration structure */
    420.  
    421.     u32 flag;
    422.     BOOL isEnable;
    423.     BOOL isBusy;
    424.     BOOL isMaster;                  /**< Master/Slave */
    425.     u8 frameSize;
    426.  
    427.     u32 totalBytes;
    428.     u32 remainingBytes;
    429.     u32 requestedBytes;
    430.     u8* sendBufferPtr;	            /**< Buffer to send (state) */
    431.     u8* recvBufferPtr;	            /**< Buffer to receive (state) */
    432.  
    433.     int (*Transfer)(struct FSpiPs_Tag spi, void* sendBuffer, void* recvBuffer, u32 byteCount);
    434.  
    435.     FSpiPs_StatusHandler statusHandler;
    436.     void* statusRef;
    437. } FSpiPs_T;
    438.  
    439. static void StubStatusHandler(void *callBackRef, u32 statusEvent,
    440.                               u32 byteCount)
    441. {
    442.     (void) callBackRef;
    443.     (void) statusEvent;
    444.     (void) byteCount;
    445. }
    446.  
    447. #define FMSH_SUCCESS          0L
    448. #define FMSH_FAILURE          1L
    449.  
    450. int FSpiPs_CfgInitialize(FSpiPs_T* spi, FSpiPs_Config_T* configPtr)
    451. {
    452.  
    453.  
    454.     spi->config = *configPtr;
    455.  
    456.     spi->isBusy = FALSE;
    457.     spi->remainingBytes = 0;
    458.     spi->requestedBytes = 0;
    459.     spi->sendBufferPtr = NULL;
    460.     spi->recvBufferPtr = NULL;
    461.  
    462.     spi->flag = 0;
    463.     spi->isEnable = FALSE;
    464.  
    465.     spi->isMaster = FALSE;
    466.  
    467.     spi->totalBytes = 0;
    468.  
    469.  
    470.     spi->statusHandler = StubStatusHandler;
    471.  
    472.     return FMSH_SUCCESS;
    473. }
    474.  
    475. void FSpiPs_Enable(FSpiPs_T* spi)
    476. {
    477.  
    478.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_SSIENR_OFFSET, 0x1);
    479.     spi->isEnable = TRUE;
    480. #if 0
    481. u32 temp=0;
    482.  
    483. //add by fzx
    484. printf("#########FMSH SPI REG IS BELOW\n");
    485. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_MSTR_OFFSET);
    486. printf("SPIPS_MSTR_OFFSET is 0x%x\n",temp);
    487.  
    488. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET);
    489. printf("SPIPS_CTRLR0_OFFSET is 0x%x\n",temp);
    490.  
    491. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_CTRLR1_OFFSET);
    492. printf("SPIPS_CTRLR1_OFFSET is 0x%x\n",temp);
    493.  
    494. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_SSIENR_OFFSET);
    495. printf("SPIPS_SSIENR_OFFSET is 0x%x\n",temp);
    496.  
    497. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_MVCR_OFFSET);
    498. printf("SPIPS_MVCR_OFFSET is 0x%x\n",temp);
    499.  
    500. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_SER_OFFSET);
    501. printf("SPIPS_SER_OFFSET is 0x%x\n",temp);
    502.  
    503. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_BAUDR_OFFSET);
    504. printf("SPIPS_BAUDR_OFFSET is 0x%x\n",temp);
    505.  
    506. temp=FMSH_ReadReg(spi->config.baseAddress, SPIPS_SR_OFFSET);
    507. printf("SPIPS_SR_OFFSET is 0x%x\n",temp);
    508. printf("############################\n");
    509. printf("############################\n");
    510. #endif
    511.  
    512. }
    513.  
    514. void FSpiPs_Disable(FSpiPs_T* spi)
    515. {
    516.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_SSIENR_OFFSET, 0x0);
    517.     spi->isEnable = FALSE;
    518. }
    519.  
    520. void FSpiPs_Mst(FSpiPs_T *spi)
    521. {
    522.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_MSTR_OFFSET, 0x1);
    523.     spi->isMaster = TRUE;
    524. }
    525.  
    526. #define SPIPS_CTRL0_SCPH_MASK       (0x1 << 6)
    527. #define SPIPS_CTRL0_SCPOL_MASK      (0x1 << 7)
    528. #define SPIPS_CTRL0_TMOD_MASK       (0x3 << 8)
    529. #define SPIPS_CTRL0_SLVOE_MASK      (0x1 << 10)
    530. #define SPIPS_CTRL0_SRL_MASK        (0x1 << 11)
    531. #define SPIPS_CTRL0_DFS32_MASK      (0x1f << 16)
    532.  
    533. #define SPIPS_CTRL0_SCPH_SHIFT      (6)
    534. #define SPIPS_CTRL0_TMOD_SHIFT      (8)
    535. #define SPIPS_CTRL0_DFS32_SHIFT     (16)
    536.  
    537. #define SPIPS_TRANSFER_STATE        (0x0)
    538. #define SPIPS_TRANSMIT_ONLY_STATE   (0x1)
    539. #define SPIPS_RECEIVE_ONLY_STATE    (0x2)
    540. #define SPIPS_EEPROM_STATE          (0x3)
    541.  
    542. int FSpiPs_SetTMod(FSpiPs_T* spi, u32 tmod)
    543. {
    544.     u32 configReg;
    545.  
    546.     if(spi->isEnable == TRUE)
    547.     {
    548.         return FMSH_FAILURE;
    549.     }
    550.     if(tmod > 3)
    551.     {
    552.         return FMSH_FAILURE;
    553.     }
    554.  
    555.     configReg = FMSH_ReadReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET);
    556.     configReg &= ~SPIPS_CTRL0_TMOD_MASK;
    557.     configReg |= (tmod << SPIPS_CTRL0_TMOD_SHIFT);
    558.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET, configReg);
    559.  
    560.     return FMSH_SUCCESS;
    561. }
    562.  
    563. int FSpiPs_SetSckMode(FSpiPs_T* spi, u32 sckMode)
    564. {
    565.     u32 configReg;
    566.  
    567.     if(spi->isEnable == TRUE)
    568.     {
    569.         return FMSH_FAILURE;
    570.     }
    571.     if(sckMode > 3)
    572.     {
    573.         return FMSH_FAILURE;
    574.     }
    575.     configReg = FMSH_ReadReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET);
    576.     configReg &= ~(SPIPS_CTRL0_SCPH_MASK | SPIPS_CTRL0_SCPOL_MASK);
    577.     configReg |= (sckMode << SPIPS_CTRL0_SCPH_SHIFT);
    578.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET, configReg);
    579.  
    580.     return FMSH_SUCCESS;
    581. }
    582.  
    583. int FSpiPs_SetSckDv(FSpiPs_T* spi, u32 sckdv)
    584. {
    585.     if(spi->isEnable == TRUE || spi->isMaster == FALSE)
    586.     {
    587.         return FMSH_FAILURE;
    588.     }
    589.  
    590.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_BAUDR_OFFSET, sckdv);
    591.  
    592.     return FMSH_SUCCESS;
    593. }
    594.  
    595. int FSpiPs_SetDFS32(FSpiPs_T* spi, u32 dfs32)
    596. {
    597.     u32 configReg;
    598.  
    599.     if(spi->isEnable == TRUE)
    600.     {
    601.         return FMSH_FAILURE;
    602.     }
    603.     if(dfs32<4 || dfs32 > 0x20)
    604.     {
    605.         return FMSH_FAILURE;
    606.     }
    607.  
    608.     configReg = FMSH_ReadReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET);
    609.     configReg &= ~SPIPS_CTRL0_DFS32_MASK;
    610.     configReg |= ((dfs32-1) << SPIPS_CTRL0_DFS32_SHIFT);
    611.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET, configReg);
    612.  
    613.     spi->frameSize = dfs32;
    614.  
    615.     return FMSH_SUCCESS;
    616. }
    617.  
    618. int FSpiPs_SetLoopBack(FSpiPs_T* spi, BOOL enable)
    619. {
    620.     u32 configReg;
    621.  
    622.     if(spi->isEnable == TRUE)
    623.     {
    624.         return FMSH_FAILURE;
    625.     }
    626.     configReg = FMSH_ReadReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET);
    627.     if(enable)
    628.     {
    629.         configReg |= SPIPS_CTRL0_SRL_MASK;
    630.     }
    631.     else
    632.     {
    633.         configReg &= ~SPIPS_CTRL0_SRL_MASK;
    634.     }
    635.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET, configReg);
    636.  
    637.     return FMSH_SUCCESS;
    638. }
    639.  
    640. int FSpiPs_SetDFNum(FSpiPs_T* spi, u32 dfNum)
    641. {
    642.     if(spi->isEnable == TRUE || spi->isMaster == FALSE)
    643.     {
    644.         return FMSH_FAILURE;
    645.     }
    646.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_CTRLR1_OFFSET, dfNum-1);
    647.  
    648.     return FMSH_SUCCESS;
    649. }
    650.  
    651. int FSpiPs_SetTxEmptyLvl(FSpiPs_T* spi, u8 tlvl)
    652. {
    653.     if(spi->isEnable == TRUE)
    654.     {
    655.         return FMSH_FAILURE;
    656.     }
    657.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_TXFTLR_OFFSET, tlvl);
    658.  
    659.     return FMSH_SUCCESS;
    660. }
    661.  
    662. int FSpiPs_SetRxFullLvl(FSpiPs_T* spi, u8 tlvl)
    663. {
    664.     if(spi->isEnable == TRUE)
    665.     {
    666.         return FMSH_FAILURE;
    667.     }
    668.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_RXFTLR_OFFSET, tlvl);
    669.  
    670.     return FMSH_SUCCESS;
    671. }
    672.  
    673. void FSpiPs_SetDMATLvl(FSpiPs_T* spi, u32 tlvl)
    674. {
    675.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_DMATDLR_OFFSET, tlvl);
    676. }
    677.  
    678. void FSpiPs_SetDMARLvl(FSpiPs_T* spi, u32 tlvl)
    679. {
    680.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_DMARDLR_OFFSET, tlvl);
    681. }
    682.  
    683. void FSpiPs_DisableIntr( FSpiPs_T* spi, u32 mask)
    684. {
    685.     u32 configReg;
    686.  
    687.     configReg = FMSH_ReadReg(spi->config.baseAddress, SPIPS_IMR_OFFSET);
    688.     configReg &= ~mask;
    689.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_IMR_OFFSET, configReg);
    690. }
    691.  
    692. int FSpiPs_SetSlave(FSpiPs_T* spi, u32 slaveNo)
    693. {
    694.     if(spi->isMaster == FALSE)
    695.     {
    696.         return FMSH_FAILURE;
    697.     }
    698.     if(slaveNo == 0)
    699.     {
    700.         FMSH_WriteReg(spi->config.baseAddress, SPIPS_SER_OFFSET, 0x0);
    701.     }
    702.     else
    703.     {
    704.         FMSH_WriteReg(spi->config.baseAddress, SPIPS_SER_OFFSET, 0x1 << (slaveNo - 1));
    705.     }
    706.  
    707.     return FMSH_SUCCESS;
    708. }
    709.  
    710. #define SPIPS_INTR_ALL              (0x3f)
    711.  
    712. int FSpiPs_Initialize_Master(FSpiPs_T* spi)
    713. {
    714.     int err = 0;
    715.  
    716.     // Check whether there is another transfer in progress. Not thread-safe
    717.     if(spi->isBusy == TRUE)
    718.     {
    719.         return FMSH_FAILURE;
    720.     }
    721.  
    722.     // Disable device
    723.     FSpiPs_Disable(spi);
    724.     // Select device as Master
    725.     FSpiPs_Mst(spi);
    726.     // CTRL (TMode, CkMode, BaudRate, DFSize, DFNum, isLoopBack)
    727.     err |= FSpiPs_SetTMod(spi, SPIPS_TRANSFER_STATE);
    728.     err |= FSpiPs_SetSckMode(spi, 3);
    729.     err |= FSpiPs_SetSckDv(spi, 120);
    730.     err |= FSpiPs_SetDFS32(spi, 8);
    731.     err |= FSpiPs_SetLoopBack(spi, FALSE);
    732.     err |= FSpiPs_SetDFNum(spi, 128);
    733.  
    734.     // Config Tx/Rx Threshold
    735.     err |= FSpiPs_SetTxEmptyLvl(spi, 20);
    736.     err |= FSpiPs_SetRxFullLvl(spi, 12);
    737.     FSpiPs_SetDMATLvl(spi, 12);
    738.     FSpiPs_SetDMARLvl(spi, 20);
    739.  
    740.     // Config IMR
    741.     FSpiPs_DisableIntr(spi, SPIPS_INTR_ALL);
    742.  
    743.     // SlaveSelect
    744.     err |= FSpiPs_SetSlave(spi, 1);
    745.  
    746.     if(err)
    747.     {
    748.         return FMSH_FAILURE;
    749.     }
    750.     // Enable device
    751.     FSpiPs_Enable(spi);
    752.  
    753.     return FMSH_SUCCESS;
    754. }
    755.  
    756. #define NREAD	(0x60)
    757. #define NWRITE	(0x61)
    758.  
    759. #define SIO (0xF0)
    760. #define STS (0xFE)
    761. #define SPG (0xFF)
    762.  
    763. #define SPIPS_SR_DCOL               (0x40)
    764. #define SPIPS_SR_TXE                (0x20)
    765. #define SPIPS_SR_RFF                (0x10)
    766. #define SPIPS_SR_RFNE               (0x08)
    767. #define SPIPS_SR_TFE                (0x04)
    768. #define SPIPS_SR_TFNF               (0x02)
    769. #define SPIPS_SR_BUSY               (0x01)
    770.  
    771. void delay_us(u32 time_us)
    772. {
    773. 	for(u32 i = 0; i < 100000; i++);
    774. }
    775.  
    776. void delay_ms(u32 time_ms)
    777. {
    778. 	for(u32 i = 0; i < 1000000; i++);
    779. }
    780.  
    781. void FSpiPs_Send(FSpiPs_T* spi, u32 Data )
    782. {
    783.     u32 count = 0;
    784.     u8 status;
    785.  
    786.     status = FMSH_ReadReg(spi->config.baseAddress, SPIPS_SR_OFFSET);
    787.     while((status & SPIPS_SR_TFNF) == 0)   /* loop if TX fifo full */
    788.     {
    789.         delay_us(1);
    790.         count++;
    791.         if(count > 10000)
    792.         {
    793.             break;
    794.         }
    795.         status = FMSH_ReadReg(spi->config.baseAddress, SPIPS_SR_OFFSET);
    796.     }
    797.  
    798.     FMSH_WriteReg(spi->config.baseAddress, SPIPS_DR_OFFSET, Data);
    799. }
    800.  
    801. u32 FSpiPs_Recv(FSpiPs_T* spi )
    802. {
    803.     u32 count = 0;
    804.     u8 status;
    805.  
    806.     status = FMSH_ReadReg(spi->config.baseAddress, SPIPS_SR_OFFSET);
    807.     while((status & SPIPS_SR_RFNE) == 0)  /* loop if RX fifo empty */
    808.     {
    809.         delay_us(1);
    810.         count++;
    811.         if(count > 10000)
    812.         {
    813.             break;
    814.         }
    815.         status = FMSH_ReadReg(spi->config.baseAddress, SPIPS_SR_OFFSET);
    816.     }
    817.  
    818.     return FMSH_ReadReg(spi->config.baseAddress, SPIPS_DR_OFFSET);
    819. }
    820.  
    821. #define SPIPS_FIFO_DEPTH            (0x20)
    822.  
    823. int FSpiPs_PolledTransfer(FSpiPs_T* spi, u8* sendBuffer, u8* recvBuffer, u32 byteCount)
    824. {
    825.     u8 tmod;
    826.  
    827.     // Check whether there is another transfer in progress. Not thread-safe
    828.     if(spi->isBusy == TRUE)
    829.     {
    830.         return FMSH_FAILURE;
    831.     }
    832.  
    833.     // Get transfer mode
    834.     tmod = (FMSH_ReadReg(spi->config.baseAddress, SPIPS_CTRLR0_OFFSET) & SPIPS_CTRL0_TMOD_MASK)
    835.         >> SPIPS_CTRL0_TMOD_SHIFT;
    836.  
    837.     if(tmod == SPIPS_TRANSFER_STATE)
    838.     {
    839.         if(sendBuffer == NULL || recvBuffer == NULL)
    840.         {
    841.             return FMSH_FAILURE;
    842.         }
    843.         spi->totalBytes = byteCount;
    844.         spi->remainingBytes = byteCount;
    845.         spi->requestedBytes = byteCount;
    846.         spi->sendBufferPtr = sendBuffer;
    847.         spi->recvBufferPtr = recvBuffer;
    848.     }
    849.     else if(tmod == SPIPS_TRANSMIT_ONLY_STATE)
    850.     {
    851.         if(sendBuffer == NULL)
    852.         {
    853.             return FMSH_FAILURE;
    854.         }
    855.         spi->totalBytes = byteCount;
    856.         spi->requestedBytes = 0;
    857.         spi->remainingBytes = byteCount;
    858.     }
    859.     else if(tmod == SPIPS_RECEIVE_ONLY_STATE)
    860.     {
    861.         if(recvBuffer == NULL)
    862.         {
    863.             return FMSH_FAILURE;
    864.         }
    865.         spi->totalBytes = byteCount;
    866.         spi->requestedBytes = byteCount;
    867.         spi->remainingBytes = 0;
    868.         /* Write one dummy data word to Tx FIFO */
    869.         FSpiPs_Send(spi, 0xff);
    870.     }
    871.     else if(tmod == SPIPS_EEPROM_STATE)
    872.     {
    873.         if(sendBuffer == NULL || recvBuffer == NULL)
    874.         {
    875.             return FMSH_FAILURE;
    876.         }
    877.         spi->totalBytes = byteCount;
    878.         spi->requestedBytes = 0;
    879.         spi->remainingBytes = byteCount;
    880.     }
    881.  
    882.     // Set the busy flag, cleared when transfer is done
    883.     spi->isBusy = TRUE;
    884.  
    885.     //disable interrupt
    886.     FSpiPs_DisableIntr(spi, SPIPS_INTR_ALL);
    887.  
    888.     //enable spi
    889.     FSpiPs_Enable(spi);
    890.  
    891.     //polling tx fifo level until transfer complete
    892.     int cnt;
    893.     u32 txLvl;
    894.     u32 txEmptyLvl = 10;
    895.     while(spi->remainingBytes !=0 || spi->requestedBytes != 0)
    896.     {
    897.         txLvl = FMSH_ReadReg(spi->config.baseAddress, SPIPS_TXFLR_OFFSET);
    898.         if(txLvl <= txEmptyLvl)
    899.         {
    900.             cnt = FMSH_ReadReg(spi->config.baseAddress, SPIPS_RXFLR_OFFSET);
    901.             while(cnt > 0 && spi->requestedBytes != 0)
    902.             {
    903.                 if(spi->frameSize == 8)
    904.                 {
    905.                     *(u8*)(spi->recvBufferPtr) = (u8)FSpiPs_Recv(spi);
    906.                 }
    907.                 else if(spi->frameSize == 16)
    908.                 {
    909.                     *(u16*)(spi->recvBufferPtr) = (u16)FSpiPs_Recv(spi);
    910.                 }
    911.                 else if(spi->frameSize == 32)
    912.                 {
    913.                     *(u32*)(spi->recvBufferPtr) = (u32)FSpiPs_Recv(spi);
    914.                 }
    915.  
    916.                 spi->recvBufferPtr += spi->frameSize >> 3;
    917.                 spi->requestedBytes -= spi->frameSize >> 3;
    918.                 cnt--;
    919.             }
    920.             cnt = SPIPS_FIFO_DEPTH - txEmptyLvl;
    921.             while(cnt > 0 && spi->remainingBytes != 0)
    922.             {
    923.                 if(spi->frameSize == 8)
    924.                 {
    925.                     FSpiPs_Send(spi, *(u8*)spi->sendBufferPtr);
    926.                 }
    927.                 else if(spi->frameSize == 16)
    928.                 {
    929.                     FSpiPs_Send(spi, *(u16*)spi->sendBufferPtr);
    930.                 }
    931.                 else if(spi->frameSize == 32)
    932.                 {
    933.                     FSpiPs_Send(spi, *(u32*)spi->sendBufferPtr);
    934.                 }
    935.                 spi->sendBufferPtr += spi->frameSize >> 3;
    936.                 spi->remainingBytes -= spi->frameSize >> 3;
    937.                 cnt--;
    938.             }
    939.         }
    940.     }
    941.  
    942.     //Clear the busy flag
    943.     spi->isBusy = FALSE;
    944.  
    945.     //disable spi
    946.     FSpiPs_Disable(spi);
    947.  
    948.     return FMSH_SUCCESS;
    949. }
    950.  
    951. #define SPIF	(0x80)
    952. #define RACK	(0x20)
    953. #define RXRDY	(0x02)
    954. #define TXRDY	(0x01
    955.  
    956. #define TIMEOUT_HANDLER	(retVal= FMSH_FAILURE);
    957.  
    958.  
    959. int writeBCM5396( FSpiPs_T *Spi_ptr,u8 page, u8 offset, u8 *pBuffer )
    960. {
    961. 	u8 data[20];
    962. 	u8 data_recv[20];
    963.         s32 retVal;
    964. 	u32 u32SendNum, u32ReqRetNum;
    965.  
    966.  
    967. 	int i;
    968. 	for(i=0;i<20;i++)
    969. 		data[i]=i;
    970. 	// Set Page
    971. 	data[0] = NWRITE;
    972. 	data[1] = SPG;
    973. 	data[2] = page;
    974. 	u32SendNum = 3;
    975. 	u32ReqRetNum = 0;
    976. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum);//pBuffer
    977. 	if( retVal != FMSH_SUCCESS )
    978. 	{
    979. 		printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    980. 	}
    981.  
    982. 	// Read STS
    983. READ_STS_1:
    984. 	data[0] = NREAD;
    985. 	data[1] = STS;
    986. 	u32SendNum = 2;
    987. 	u32ReqRetNum = 1;
    988. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    989.  
    990. 	if( retVal == FMSH_SUCCESS )
    991. 	{
    992. 		if((data_recv[2] & SPIF)==0)//( workBuf[2] & SPIF )
    993. 		{
    994. 			// Set Page
    995. 			data[0] = NWRITE;
    996. 			data[1] = SPG;
    997. 			data[2] = page;
    998. 			u32SendNum = 3;
    999. 			u32ReqRetNum = 0;
    1000. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1001. 			if( retVal != FMSH_SUCCESS )
    1002. 			{
    1003. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1004. 			}
    1005.  
    1006. 			// Write Data
    1007. 			data[0] = NWRITE;
    1008. 			data[1] = offset;
    1009. 			data[2] = pBuffer[0];
    1010. 			data[3] = pBuffer[1];
    1011. 			u32SendNum = 4;
    1012. 			u32ReqRetNum = 0;//1;
    1013. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1014. 			if( retVal != FMSH_SUCCESS )
    1015. 			{
    1016. 				printf("Call XSpiPs_PT_SL 2 Failed\n\r");
    1017. 			}
    1018.  
    1019. 		}
    1020. 		else
    1021. 		{
    1022. 			TIMEOUT_HANDLER;
    1023. 			printf( "Timeout 1 Occured!\n\r" );
    1024. 			delay_ms(100);
    1025.  
    1026. 			// Set Page
    1027. 			data[0] = NWRITE;
    1028. 			data[1] = SPG;
    1029. 			data[2] = page;
    1030. 			u32SendNum = 3;
    1031. 			u32ReqRetNum = 0;
    1032. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1033. 			if( retVal != FMSH_SUCCESS )
    1034. 			{
    1035. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1036. 			}
    1037.  
    1038. 			goto READ_STS_1;
    1039. 		}
    1040. 	}
    1041. 	else
    1042. 		printf("Call XSpiPs_PT_SL 4 Failed\n\r");
    1043.  
    1044. 	return retVal;
    1045. }
    1046.  
    1047. int readBCM5396(FSpiPs_T *Spi_ptr, u8 page, u8 offset, u8 *pBuffer )
    1048. {
    1049. //	_BCM_CMD_ bcmCmd;
    1050. 	u8 data[8];//u8Idx;
    1051.         u8 data_recv[8] = {0};
    1052. 	s32 retVal;
    1053. 	u32 u32SendNum, u32ReqRetNum;
    1054.  
    1055.  
    1056. 	// Set Page
    1057. 	data[0] = NWRITE;
    1058. 	data[1] = SPG;
    1059. 	data[2] = page;
    1060.  
    1061. 	u32SendNum = 3;
    1062. 	u32ReqRetNum = 0;
    1063. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum);
    1064. 	if( retVal != FMSH_SUCCESS )
    1065. 	{
    1066. 		printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1067. 	}
    1068.         delay_ms(10);
    1069. 	// Read STS
    1070. READ_STS_1:
    1071.  
    1072.         data[0] = NREAD;
    1073. 	data[1] = STS;
    1074. 	u32SendNum = 2;
    1075. 	u32ReqRetNum = 1;
    1076. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1077.          delay_ms(10);
    1078.  
    1079. 	if( retVal == FMSH_SUCCESS )
    1080. 	{
    1081. 		if( (data_recv[2] & SPIF)==0)
    1082. 		{
    1083. 			// Set Page
    1084. 			data[0] = NWRITE;
    1085. 			data[1] = SPG;
    1086. 			data[2] = page;
    1087. 			u32SendNum = 3;
    1088. 			u32ReqRetNum = 0;
    1089. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1090. 			if( retVal != FMSH_SUCCESS )
    1091. 			{
    1092. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1093. 			}
    1094.  
    1095. 			// Set Offset in Page, "Null" operation :)
    1096. 			data[0] = NREAD;
    1097. 			data[1] = offset;
    1098. 			u32SendNum = 2;
    1099. 			u32ReqRetNum = 1;
    1100. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1101. 			if( retVal != FMSH_SUCCESS )
    1102. 			{
    1103. 				printf("Call XSpiPs_PT_SL 2 Failed\n\r");
    1104. 			}
    1105.  
    1106.  
    1107. 			// Read STS
    1108. READ_STS_2:
    1109.                         data[0] = NREAD;
    1110.                         data[1] = STS;
    1111. 			u32SendNum = 2;
    1112. 			u32ReqRetNum = 1;
    1113. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1114. 			if( retVal == FMSH_SUCCESS )
    1115. 			{
    1116. 				if( data_recv[2] & RACK )
    1117. 				{
    1118. 					/*
    1119. 					bcmCmd.cmd = NREAD;
    1120. 					bcmCmd.regAdrs = SIO;
    1121. 					*/
    1122. 					data[0] = NREAD;
    1123. 				        data[1] = SIO;
    1124. 					u32SendNum = 2;
    1125. 					u32ReqRetNum = 4;
    1126. 					retVal = FSpiPs_PolledTransfer(Spi_ptr,data,pBuffer,u32SendNum+u32ReqRetNum);
    1127. 				}
    1128. 				else
    1129. 				{
    1130. 					TIMEOUT_HANDLER;
    1131. 					printf( "Timeout 2 Occured!\n\r" );
    1132. 					delay_ms(10);
    1133. 					// Set Page
    1134. 					data[0] = NWRITE;
    1135. 					data[1] = SPG;
    1136. 					data[2] = page;
    1137. 					u32SendNum = 3;
    1138. 					u32ReqRetNum = 0;
    1139. 					retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1140. 					if( retVal != FMSH_SUCCESS )
    1141. 					{
    1142. 						printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1143. 					}
    1144.  
    1145. 					goto READ_STS_2;
    1146. 				}
    1147.  
    1148. 			}
    1149. 			else
    1150. 				printf("Call XSpiPs_PT_SL 3 Failed\n\r");
    1151. 		}
    1152. 		else
    1153. 		{
    1154. 			TIMEOUT_HANDLER;
    1155. 			printf( "Timeout 1 Occured!\n\r" );
    1156. 			delay_ms(100);
    1157.  
    1158. 			// Set Page
    1159. 			data[0] = NWRITE;
    1160. 			data[1] = SPG;
    1161. 			data[2] = page;
    1162. 			u32SendNum = 3;
    1163. 			u32ReqRetNum = 0;
    1164. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,pBuffer,u32SendNum+u32ReqRetNum);
    1165. 			if( retVal != FMSH_SUCCESS )
    1166. 			{
    1167. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1168. 			}
    1169.  
    1170. 			goto READ_STS_1;
    1171. 		}
    1172. 	}
    1173. 	else
    1174. 		printf("Call XSpiPs_PT_SL 4 Failed\n\r");
    1175.  
    1176. 	return retVal;
    1177. }
    1178.  
    1179. int writeBCM5396_2( FSpiPs_T *Spi_ptr,u8 page, u8 offset, u8 *pBuffer )
    1180. {
    1181. 	u8 data[20];
    1182. 	u8 data_recv[20];
    1183.         s32 retVal;
    1184. 	u32 u32SendNum, u32ReqRetNum;
    1185.         
    1186.         
    1187. 	int i;
    1188. 	for(i=0;i<20;i++)
    1189. 		data[i]=i;
    1190. 	// Set Page
    1191. 	data[0] = NWRITE;
    1192. 	data[1] = SPG;
    1193. 	data[2] = page;
    1194. 	u32SendNum = 3;
    1195. 	u32ReqRetNum = 0;
    1196. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum);//pBuffer
    1197. 	if( retVal != FMSH_SUCCESS )
    1198. 	{
    1199. 		printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1200. 	}
    1201.  
    1202. 	// Read STS
    1203. READ_STS_1:
    1204. 	data[0] = NREAD;
    1205. 	data[1] = STS;
    1206. 	u32SendNum = 2;
    1207. 	u32ReqRetNum = 1;
    1208. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1209. 	//
    1210. 	if( retVal == FMSH_SUCCESS ) 
    1211. 	{
    1212. 		if((data_recv[2] & SPIF)==0)//( workBuf[2] & SPIF )
    1213. 		{
    1214. 			// Set Page
    1215. 			data[0] = NWRITE;
    1216. 			data[1] = SPG;
    1217. 			data[2] = page;
    1218. 			u32SendNum = 3;
    1219. 			u32ReqRetNum = 0;
    1220. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1221. 			if( retVal != FMSH_SUCCESS )
    1222. 			{
    1223. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1224. 			}
    1225.  
    1226. 			// Write Data
    1227. 			data[0] = NWRITE;
    1228. 			data[1] = offset;
    1229. 			data[2] = pBuffer[0];  
    1230. 			u32SendNum = 3;
    1231. 			u32ReqRetNum = 0;//1;
    1232. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1233. 			if( retVal != FMSH_SUCCESS )
    1234. 			{
    1235. 				printf("Call XSpiPs_PT_SL 2 Failed\n\r");
    1236. 			}
    1237.  
    1238. 		}
    1239. 		else
    1240. 		{
    1241. 			TIMEOUT_HANDLER;
    1242. 			printf( "Timeout 1 Occured!\n\r" );
    1243. 			delay_ms(50);
    1244.  
    1245. 			// Set Page
    1246. 			data[0] = NWRITE;
    1247. 			data[1] = SPG;
    1248. 			data[2] = page;
    1249. 			u32SendNum = 3;
    1250. 			u32ReqRetNum = 0;
    1251. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1252. 			if( retVal != FMSH_SUCCESS )
    1253. 			{
    1254. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1255. 			}
    1256.  
    1257. 			goto READ_STS_1;
    1258. 		}
    1259. 	}
    1260. 	else
    1261. 		printf("Call XSpiPs_PT_SL 4 Failed\n\r");
    1262.  
    1263. 	return retVal;
    1264. }
    1265.  
    1266. int writeBCM5396_4( FSpiPs_T *Spi_ptr,u8 page, u8 offset, u8 *pBuffer )
    1267. {
    1268. 	u8 data[20];
    1269. 	u8 data_recv[20];
    1270.         s32 retVal;
    1271. 	u32 u32SendNum, u32ReqRetNum;
    1272.         
    1273.         
    1274. 	int i;
    1275. 	for(i=0;i<20;i++)
    1276. 		data[i]=i;
    1277. 	// Set Page
    1278. 	data[0] = NWRITE;
    1279. 	data[1] = SPG;
    1280. 	data[2] = page;
    1281. 	u32SendNum = 3;
    1282. 	u32ReqRetNum = 0;
    1283. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum);//pBuffer
    1284. 	if( retVal != FMSH_SUCCESS )
    1285. 	{
    1286. 		printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1287. 	}
    1288.  
    1289. 	// Read STS
    1290. READ_STS_1:
    1291. 	data[0] = NREAD;
    1292. 	data[1] = STS;
    1293. 	u32SendNum = 2;
    1294. 	u32ReqRetNum = 1;
    1295. 	retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1296. 	//
    1297. 	if( retVal == FMSH_SUCCESS ) 
    1298. 	{
    1299. 		if((data_recv[2] & SPIF)==0)//( workBuf[2] & SPIF )
    1300. 		{
    1301. 			// Set Page
    1302. 			data[0] = NWRITE;
    1303. 			data[1] = SPG;
    1304. 			data[2] = page;
    1305. 			u32SendNum = 3;
    1306. 			u32ReqRetNum = 0;
    1307. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1308. 			if( retVal != FMSH_SUCCESS )
    1309. 			{
    1310. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1311. 			}
    1312.  
    1313. 			// Write Data
    1314. 			data[0] = NWRITE;
    1315. 			data[1] = offset;
    1316. 			data[2] = pBuffer[0];  
    1317. 			u32SendNum = 6;
    1318. 			u32ReqRetNum = 0;//1;
    1319. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1320. 			if( retVal != FMSH_SUCCESS )
    1321. 			{
    1322. 				printf("Call XSpiPs_PT_SL 2 Failed\n\r");
    1323. 			}
    1324.  
    1325. 		}
    1326. 		else
    1327. 		{
    1328. 			TIMEOUT_HANDLER;
    1329. 			printf( "Timeout 1 Occured!\n\r" );
    1330. 			delay_ms(50);
    1331.  
    1332. 			// Set Page
    1333. 			data[0] = NWRITE;
    1334. 			data[1] = SPG;
    1335. 			data[2] = page;
    1336. 			u32SendNum = 3;
    1337. 			u32ReqRetNum = 0;
    1338. 			retVal = FSpiPs_PolledTransfer(Spi_ptr,data,data_recv,u32SendNum+u32ReqRetNum);
    1339. 			if( retVal != FMSH_SUCCESS )
    1340. 			{
    1341. 				printf("Call XSpiPs_PT_SL 1 Failed\n\r");
    1342. 			}
    1343.  
    1344. 			goto READ_STS_1;
    1345. 		}
    1346. 	}
    1347. 	else
    1348. 		printf("Call XSpiPs_PT_SL 4 Failed\n\r");
    1349.  
    1350. 	return retVal;
    1351. }
    1352.  
    1353. FSpiPs_T spi;
    1354. FSpiPs_T Spi[2];
    1355.  
    1356. int port_vlan_set(unsigned int port, unsigned int mask)
    1357. {
    1358.       u8 workBuf[10];
    1359.       int Status        = 0;
    1360.       int offset        = 0;
    1361.       
    1362.       offset = port*4;
    1363.      // printf("--------Set Port Vlan:port:%d-offset:%0x-mask:%0x---------\n\r", port, mask);
    1364.       
    1365.       workBuf[0] = (mask&0x000000ff);
    1366.       workBuf[1] = (mask&0x0000ff00)>>8;
    1367.       workBuf[2] = (mask&0x00010000)>>16;
    1368.       
    1369.       Status = writeBCM5396_4(&spi, 0x31, offset, workBuf); 
    1370.       
    1371.       return Status;
    1372. }
    1373. /***************************************BOARD SW1706 JEM5396 REG READ/WRITE*****************************/
    1374.  
    1375. void testwrite5396(int port, unsigned int offset ,unsigned int value)
    1376. {
    1377.  
    1378. 	u8 workBuf[10];
    1379. 	workBuf[0]=value & 0xff;
    1380. 	workBuf[1]=(value>>8) & 0xff;
    1381. 	writeBCM5396(&spi, port, offset, workBuf);
    1382. 	udelay(1000);
    1383.         readBCM5396(&spi, port, offset, workBuf );
    1384. 	printf("port=%d,offset=%xh,data=0x%x\n\r",port,offset,workBuf[2]);
    1385. 	printf("port=%d,offset=%xh,data=0x%x\n\r",port,offset,workBuf[3]);
    1386. }
    1387. void testread5396()
    1388. {
    1389.  
    1390. 	u8 workBuf[10];
    1391.        	readBCM5396(&spi, 2, 0x30, workBuf);
    1392. 	printf("5396 Mode_ID=0x%x\n\r", workBuf[2]);
    1393. }
    1394.  
    1395. int ckoff_spi_5396()
    1396. {
    1397.  
    1398. 	int ret = 0;
    1399. 	int Status = 0;
    1400. 	u8 workBuf[10];
    1401. 	int i=0;
    1402.  
    1403. 	/*init spi and read bcm5396 device id*/
    1404.  
    1405. 	FSpiPs_Config_T *spi_cfgptr;
    1406.  
    1407. 	spi_cfgptr = FSpiPs_LookupConfig(0);
    1408.  
    1409. 	ret = FSpiPs_CfgInitialize(&spi, spi_cfgptr);
    1410.  
    1411. 	if(ret == FMSH_SUCCESS)
    1412. 	{
    1413. 		printf("5396 Spi Init Success!\n\r");
    1414. 	}	
    1415. 	else
    1416. 	{
    1417. 	    printf("5396 Spi Init Failed!\n\r");
    1418. 	    return -1;
    1419. 	}
    1420.  
    1421. 	/*Init master*/
    1422. 	ret = FSpiPs_Initialize_Master(&spi);
    1423. 	if(ret == FMSH_SUCCESS)
    1424. 	{
    1425. 		printf("spi Init Master Success!\n\r");
    1426. 	}
    1427. 	else
    1428. 	{
    1429. 		printf("spi Init Master Failed!\n\r");
    1430. 		return -1;
    1431. 	}	
    1432. 	
    1433. 	workBuf[0]=0xf1;
    1434. 	workBuf[1]=0x28;
    1435. 	workBuf[2]=0;
    1436.  
    1437.  
    1438. 	for(i=0x10;i<=0x1f;i++)
    1439. 	{
    1440. 		Status = writeBCM5396(&spi, i, 0x12, workBuf );
    1441. 	}
    1442.  
    1443.  
    1444. 	workBuf[0]=0xf0;
    1445. 	workBuf[1]=0x28;
    1446. 	workBuf[2]=0;
    1447.  
    1448.  
    1449. 	for(i=0x10;i<=0x1f;i++)
    1450. 	{
    1451. 		Status = writeBCM5396(&spi, i, 0x12, workBuf );
    1452. 	}
    1453.  
    1454.  
    1455. 	printf("JEM5396 CHECK OFF DONW\n");
    1456.  
    1457.  
    1458. 	return 0;
    1459. }
    1460.  
    1461. /***************************************BOARD SW1706 JEM5396 REG READ/WRITE*****************************/
    1462. int init_spi_5396()
    1463. {
    1464.  
    1465. 	int ret = 0;
    1466. 	int Status = 0;
    1467. 	u8 workBuf[10];
    1468. 	int i=0;
    1469.  
    1470. 	/*init spi and read bcm5396 device id*/
    1471. #if 0
    1472. 	FSpiPs_Config_T *spi_cfgptr;
    1473.  
    1474. 	spi_cfgptr = FSpiPs_LookupConfig(0);
    1475.  
    1476. 	ret = FSpiPs_CfgInitialize(&spi, spi_cfgptr);
    1477.  
    1478. 	if(ret == FMSH_SUCCESS)
    1479. 	{
    1480. 		printf("5396 Spi Init Success!\n\r");
    1481. 	}	
    1482. 	else
    1483. 	{
    1484. 	    printf("5396 Spi Init Failed!\n\r");
    1485. 	    return -1;
    1486. 	}
    1487.  
    1488. 	/*Init master*/
    1489. 	ret = FSpiPs_Initialize_Master(&spi);
    1490. 	if(ret == FMSH_SUCCESS)
    1491. 	{
    1492. 		printf("spi Init Master Success!\n\r");
    1493. 	}
    1494. 	else
    1495. 	{
    1496. 		printf("spi Init Master Failed!\n\r");
    1497. 		return -1;
    1498. 	}	
    1499. #endif
    1500. 	Status=readBCM5396(&spi, 2, 0x30, workBuf);
    1501. 	printf("5396 Mode_ID=0x%x\n\r", workBuf[2]);
    1502.  
    1503. 	Status=readBCM5396(&spi, 2, 0x40, workBuf);
    1504. 	printf("5396 Reversion_ID=0x%x\n\r", workBuf[2]);
    1505.  
    1506. /***************************************JEM5396 CONFIG*****************************/
    1507. 	
    1508.  
    1509. 	/**PORT N STATE OVERRIDE REGISTER [0:15] (PAGE 00H: ADDRESS 60H–6FH) **/
    1510. 	/**强制千兆全双工模式**/
    1511. 	for(i=0x60;i<=0x6f;i++)
    1512. 	{
    1513. 		workBuf[0] = 0x8b;
    1514. 		workBuf[1] = 0x0;
    1515. 		if(i==0x65)
    1516. 		{
    1517. 			continue;
    1518. 		}
    1519. 		writeBCM5396_2(&spi, 0, i, workBuf);
    1520. 	}
    1521.  
    1522.  
    1523. 	workBuf[0]=0xf0;
    1524. 	workBuf[1]=0x1;
    1525. 	workBuf[2]=0;
    1526.  
    1527.  
    1528. 	for(i=0x10;i<=0x1f;i++)
    1529. 	{
    1530.  
    1531. 		if(i==0x15)
    1532. 		{
    1533. 			continue;
    1534. 		}
    1535.  
    1536. 		Status = writeBCM5396(&spi, i, 0x20, workBuf );
    1537. 	}
    1538.  
    1539. 	workBuf[0]=0x40;
    1540. 	workBuf[1]=0x13;
    1541. 	workBuf[2]=0;
    1542.  
    1543.  
    1544. 	for(i=0x10;i<=0x1f;i++)
    1545. 	{
    1546.  
    1547. 		if(i==0x15)
    1548. 		{
    1549. 			continue;
    1550. 		}
    1551. 		Status = writeBCM5396(&spi, i, 0x0, workBuf );
    1552. 	}
    1553.  
    1554.  
    1555. 	printf("Set Port 5 CONNECT TO ZYNQ SPEED FIXED 1000M\n");
    1556.  
    1557. 	workBuf[0] = 0x8b;
    1558. 	workBuf[1] = 0x0;
    1559. 	writeBCM5396_2(&spi, 0, 0x65, workBuf);  
    1560.  
    1561.  
    1562. 	workBuf[0] = 0x40;
    1563. 	workBuf[1] = 0x1;  
    1564. 	Status = writeBCM5396(&spi, 0x15, 0x0, workBuf );  
    1565.  
    1566. 	printf("*****************Read SPI Reg of 5396******************\r\n");
    1567. 	printf("---BMC Status Registers(PAGE 0x10-0x1F)---\n");
    1568. 	for(i=0x10;i<=0x1f;i++)
    1569. 	{
    1570. 		  Status = readBCM5396(&spi, i, 0x28, workBuf );
    1571. 		  printf("port=%d,offset=0x28,data=0x%x\n",(i-0x10),workBuf[2]);
    1572. 		  printf("port=%d,offset=0x29,data=0x%x\n",(i-0x10),workBuf[3]);
    1573.     	}
    1574.  
    1575. 	printf("---BMC Status Registers(PAGE 0x10-0x1F)---\n\r");
    1576. 	for(i=0x10;i<=0x1f;i++)
    1577. 	{
    1578. 		  Status = readBCM5396(&spi, i, 0x20, workBuf );
    1579. 		  printf("port=%d,offset=0x20,data=0x%x\n\r",(i-0x10),workBuf[2]);
    1580. 		  printf("port=%d,offset=0x21,data=0x%x\n\r",(i-0x10),workBuf[3]);
    1581.     	}
    1582.  
    1583.  
    1584. #if 0
    1585. 	workBuf[0]=0x00;
    1586. 	workBuf[1]=0x00;
    1587. 	workBuf[2]=0x00;
    1588. 	Status =writeBCM5396(&spi, 0x31, 0x00, workBuf);//Port 0
    1589. 	Status =writeBCM5396(&spi, 0x31, 0x04, workBuf);//Port 1
    1590. 	Status =writeBCM5396(&spi, 0x31, 0x08, workBuf);//Port 2
    1591. 	Status =writeBCM5396(&spi, 0x31, 0x0c, workBuf);//Port 3
    1592. 	Status =writeBCM5396(&spi, 0x31, 0x10, workBuf);//Port 4
    1593. 	Status =writeBCM5396(&spi, 0x31, 0x14, workBuf);//Port 5
    1594. 	Status =writeBCM5396(&spi, 0x31, 0x18, workBuf);//Port 6
    1595. 	Status =writeBCM5396(&spi, 0x31, 0x1c, workBuf);//Port 7
    1596. 	Status =writeBCM5396(&spi, 0x31, 0x20, workBuf);//Port 8
    1597. 	Status =writeBCM5396(&spi, 0x31, 0x24, workBuf);//Port 9
    1598. 	Status =writeBCM5396(&spi, 0x31, 0x28, workBuf);//Port 10
    1599. 	Status =writeBCM5396(&spi, 0x31, 0x2c, workBuf);//Port 11
    1600. 	Status =writeBCM5396(&spi, 0x31, 0x30, workBuf);//Port 12
    1601. 	Status =writeBCM5396(&spi, 0x31, 0x34, workBuf);//Port 13
    1602. 	Status =writeBCM5396(&spi, 0x31, 0x38, workBuf);//Port 14
    1603. 	Status =writeBCM5396(&spi, 0x31, 0x3c, workBuf);//Port 15
    1604. 	Status =writeBCM5396(&spi, 0x31, 0x40, workBuf);//Port 15
    1605. 	printf("5396 ALL Port Disconnect\n\r");
    1606. #endif
    1607. 	return 0;
    1608. }
    1609.  
    1610.  
    1611. void FSlcrPs_setBitTo1(u32 baseAddr, u32 offSet,u32 bit_num)
    1612. {
    1613.     u32 value = 0;
    1614.     //First get the current value of the register
    1615.     value = FMSH_ReadReg(baseAddr, offSet);
    1616.     //Then write the given bit of data as 1
    1617.     value |= (1 << bit_num);
    1618.     //Finally, write the modified data to the register
    1619.     FMSH_WriteReg(baseAddr, offSet, value);
    1620. }
    1621. void FSlcrPs_setBitTo0(u32 baseAddr, u32 offSet,u32 bit_num)
    1622. {
    1623.     u32 value = 0;
    1624.     //First get the current value of the register
    1625.     value = FMSH_ReadReg(baseAddr, offSet);
    1626.     //Then write the given bit of data as 0
    1627.     value &= ~(1 << bit_num);
    1628.     //Finally, write the modified data to the register
    1629.     FMSH_WriteReg(baseAddr, offSet, value);
    1630. }
    1631.  
    1632. void FSlcrPs_unlock(void)
    1633. {
    1634.     FMSH_WriteReg(FPS_SLCR_BASEADDR,SLCR_UNLOCK,0xDF0D767B);   //SLCR UNLOCK
    1635. }
    1636. void FSlcrPs_lock(void)
    1637. {
    1638.     FMSH_WriteReg(FPS_SLCR_BASEADDR,SLCR_LOCK,0xDF0D767B);   //SLCR LOCK
    1639. }
    1640. void FSlcrPs_ipSetRst(u32 rst_id, u32 rst_mode)
    1641. {
    1642.     FSlcrPs_unlock();
    1643.     FSlcrPs_setBitTo1(FPS_SLCR_BASEADDR,rst_id,rst_mode);
    1644.     FSlcrPs_lock();
    1645. }
    1646. void FSlcrPs_ipReleaseRst(u32 rst_id, u32 rst_mode)
    1647. {
    1648.     FSlcrPs_unlock();
    1649.     FSlcrPs_setBitTo0(FPS_SLCR_BASEADDR,rst_id,rst_mode);
    1650.     FSlcrPs_lock();
    1651. }
    1652. void FSpiPs_Reset(FSpiPs_T* spi)
    1653. {
    1654.     if(spi->config.deviceId == FPS_SPI0_DEVICE_ID)
    1655.     {
    1656.         FSlcrPs_ipSetRst(SLCR_SPI0_CTRL, SPI0_APB_RST);
    1657.         FSlcrPs_ipSetRst(SLCR_SPI0_CTRL, SPI0_REF_RST);
    1658.         FSlcrPs_ipReleaseRst(SLCR_SPI0_CTRL, SPI0_APB_RST);
    1659.         FSlcrPs_ipReleaseRst(SLCR_SPI0_CTRL, SPI0_REF_RST);
    1660.     }
    1661.     else if(spi->config.deviceId == FPS_SPI1_DEVICE_ID)
    1662.     {
    1663.         FSlcrPs_ipSetRst(SLCR_SPI1_CTRL, SPI1_APB_RST);
    1664.         FSlcrPs_ipSetRst(SLCR_SPI1_CTRL, SPI1_REF_RST);
    1665.         FSlcrPs_ipReleaseRst(SLCR_SPI1_CTRL, SPI1_APB_RST);
    1666.         FSlcrPs_ipReleaseRst(SLCR_SPI1_CTRL, SPI1_REF_RST);
    1667.     }
    1668. }

    配置完成后，网络就能ping通了

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  • 原文地址：https://blog.csdn.net/jj12345jj198999/article/details/134525159