【【RAM的verilog 代码 + testbench】】

RAM的verilog 代码 + testbench

RAM.v

//DUal ended RAM 
module RAM #(
    parameter     WIDTH      =     8   ,
    parameter     DEPTH      =     16  ,
    parameter     ADD_WIDTH  =     clogb2(DEPTH) 
)(
    input                       wr_clk         ,
    input                       rd_clk         ,
    input                       wr_en          ,
    input                       rd_en          ,
    input      [WIDTH-1 : 0 ]      din         ,
    input      [ADD_WIDTH-1 : 0]   wr_address  ,
    output reg [WIDTH-1 : 0 ]      dout        ,
    input      [ADD_WIDTH-1 : 0]   rd_address  
);


//==================================================================================\\
//       define  parameter   and  internal   signal                                 \\
//==================================================================================\\

reg [WIDTH - 1 : 0 ] ram [DEPTH - 1 : 0] ; 





//==================================================================================\\
//                              next is  main code                                  \\
//==================================================================================\\


function integer clogb2  ;
input [31:0] value  ;
begin 
    value = value - 1 ;
    for(clogb2 = 0 ; value > 0 ; clogb2 = clogb2 + 1)
    value = value >> 1 ; 
end
endfunction 


// write  
always@(posedge wr_clk) 
begin 
    if(wr_en) begin 
        ram[wr_address] <= din ;
    end
end 

//read 
always@(posedge rd_clk) 
begin 
    if(rd_en) begin 
        dout <= ram[rd_address] ;
    end
end 
endmodule 
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RAM_tb .v

`timescale 1ns/1ps

module RAM_tb #(
    parameter     WIDTH      =     8  ,
    parameter     DEPTH     =      8  ,
    parameter     ADD_WIDTH  =     3
  );
  reg                      wr_clk         ;
  reg                      rd_clk         ;
  reg                      wr_en          ;
  reg                      rd_en          ;
  reg     [7 : 0]          din            ;
  reg     [2 : 0]          wr_address     ;
  reg     [2 : 0]          rd_address     ;
  wire    [7: 0 ]          dout           ;



  RAM#(
       .WIDTH       ( WIDTH ),
       .DEPTH       ( DEPTH ),
       .ADD_WIDTH   ( ADD_WIDTH )
     )u_RAM(
       .wr_clk      ( wr_clk      ),
       .rd_clk      ( rd_clk      ),
       .wr_en       ( wr_en       ),
       .rd_en       ( rd_en       ),
       .din         ( din         ),
       .wr_address  ( wr_address  ),
       .dout        ( dout        ),
       .rd_address  ( rd_address  )
     );






  always     #10      wr_clk   =   ~wr_clk    ;
  always     #10      rd_clk   =   ~rd_clk    ;

  initial
    begin

      wr_clk     = 0 ;
      rd_clk     = 0 ;
      wr_address = 0 ;
      rd_address = 0 ;
      din        = 1 ;

      wr_en  =  0 ;
      rd_en  =  0 ;


      #10
       wr_en  =  1 ;
      rd_en  =  1 ;

      #10
       wr_en  =  0 ;
      rd_en  =  0 ;

      #10
       wr_en  =   1 ;
       rd_en  =   1 ; 
      repeat(7)
      begin
        @(posedge wr_clk)
         begin

           wr_address = wr_address +1 ;
           din = din +1 ;

         end
       end
      #10


       repeat(7)
       begin 
        @(posedge rd_clk)
         rd_address = rd_address+ 1 ;
       end
     end
   endmodule
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