AD9371 官方例程

AD9371 系列快速入口

AD9371+ZCU102 移植到 ZCU106 ： AD9371 官方例程构建及单音信号收发

ad9371_tx_jesd -->util_ad9371_xcvr接口映射： AD9371 官方例程之 tx_jesd 与 xcvr接口映射

AD9371 官方例程 时钟间的关系与生成 ： AD9371 官方例程HDL详解之JESD204B TX侧时钟生成（一）

JESD204B相关IP端口信号 ： AD9371 官方例程HDL JESD204B相关IP端口信号

裸机程序配置 AD9528、AD9371、FPGA IP 和主函数梳理： AD9371 官方例程裸机SW 和 HDL配置概述（一）

裸机程序配置 AD9528、AD9371、FPGA IP 和主函数梳理： AD9371 官方例程裸机SW 和 HDL配置概述（二）

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前言

项目构建基本流程和AD9361差不多，由于官方使用的ZCU102，记录下移植遇到的一些问题

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一、HDL方面

1. ZYNQ 核根据ZCU106平台修改（参考UG1244 ZCU106 Evaluation Board），尤其注意DDR的配置（参考美光 MTA4ATF51264HZ）

2.dacfifo 深度 要修改 ，地址位宽 小于等于16，zcu102中 fifo 128位数据 深度2^17 需要16.7Mb ，ZU9EG BRAM 32Mb可以满足 , zcu106 BRAM 11Mb，16.7Mb 超出了106能力 ，深度改成16就可以了

3. XDC引脚要修改正确

示例如下：

set_property  -dict {PACKAGE_PIN  U2   } [get_ports rx_data_p[0]]                                      ; ## A02  FMC_HPC0_DP1_M2C_P
set_property  -dict {PACKAGE_PIN  U1   } [get_ports rx_data_n[0]]                                      ; ## A03  FMC_HPC0_DP1_M2C_N
set_property  -dict {PACKAGE_PIN  P4   } [get_ports rx_data_p[1]]                                      ; ## A06  FMC_HPC0_DP2_M2C_P
set_property  -dict {PACKAGE_PIN  P3   } [get_ports rx_data_n[1]]                                      ; ## A07  FMC_HPC0_DP2_M2C_N
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4. RX接收不到正弦，测试发现TX有问题，HDL侧修改方案

axi_ad9371_dacfifo 中 dac_rst_int_s 应该在dac_xfer_req 上升沿有效，代码也产生了上升沿，但是 assign dac_rst_int_s = dac_xfer_req | dac_rst;用错了信号

  assign dac_xfer_posedge_s = ~dac_xfer_req_d & dac_xfer_req;

  // we can reset the DAC side at each positive edge of xfer_req, even if
  // sometimes the reset is redundant
  assign dac_rst_int_s = dac_xfer_req | dac_rst;
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做如下修改可以正确发送接收正弦波

  assign dac_rst_int_s = dac_xfer_posedge_s | dac_rst;
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二、SW方面

1. 不使用iio时，确保所有需要的 .c 和 .h文件都添加进来

需要的头文件如下

2. 添加#define XPS_BOARD_ZCU102

默认的是 zynq7000 系列，ZCU106是 Zynq UltraScale+ ，和102一样 GPIO 有78个 ，而不是7000系列的54个

3. app_config.h打开 #define DMA_EXAMPLE

通过DDR 发送 接收正弦信号

4. 打印RX数据

接收数据 存到 adc_buffer 后 ，添加下列代码 ，测试知道 I1、Q1 是 RX1 路信号 ，I2、Q2 是 RX2 路信号

具体 I 路数据在高16位，还是低16位，还未验证，参考 AD9371 官方例程之 tx_jesd 与 xcvr接口映射 和 AD9371 Crossbar

		uint16_t index;
	    uint32_t data_1,data_2;
	    uint16_t Q1,I1,Q2,I2;

	    for(index =0; index < 8192; index += 1)
	    {
	    	// RX1
	    	data_1 =Xil_In32(adc_buffer+ index*(4));
	    	// RX2
	    	data_2 =Xil_In32(adc_buffer+2+ index*(4));

	    	I1 = (data_1) & 0xFFFF;
	    	Q1 = (data_1 >> 16) & 0xFFFF;

	    	I2 = (data_2) & 0xFFFF;
	    	Q2 = (data_2 >> 16) & 0xFFFF;
	    	printf("%d,%d\n",(signed short)I1,(signed short)Q1);
	    //	printf("%d,%d\n",(signed short)I2,(signed short)Q2);
	    }
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5. RX接收不到正弦，测试发现TX有问题，SW侧修改方案

该方法可以不修改HDL以接收数据，通过 拉高 axi_ad9371_dacfifo 的 dac_fifo_bypass 信号，把dacfifo 旁路 ，使用PL DDR， dac_fifo_bypass (gpio_o[60])信号 连接到EMIO 60 引脚

在 common.c 通过以下代码，只要拉高 DAC_GPIO_PLDDR_BYPASS 就可以


最终接收到正确的正弦波

---

总结

打印信息及部分接收数据如下：

Please wait...
rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (122880000 Hz)
rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
MCS successful
CLKPLL locked
AD9371 ARM version 5.2.2
PLLs locked
Calibrations completed successfully
tx_adxcvr: OK (4915200 kHz)
rx_adxcvr: OK (4915200 kHz)
rx_os_adxcvr: OK (4915200 kHz)
rx_jesd status:
	Link is enabled
	Measured Link Clock: 122.882 MHz
	Reported Link Clock: 122.880 MHz
	Lane rate: 4915.200 MHz
	Lane rate / 40: 122.880 MHz
	LMFC rate: 3.840 MHz
	Link status: DATA
	SYSREF captured: Yes
	SYSREF alignment error: No
rx_jesd lane 0 status:
Errors: 0
	CGS state: DATA
	Initial Frame Synchronization: Yes
	Lane Latency: 1 Multi-frames and 60 Octets
	Initial Lane Alignment Sequence: Yes
	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
	FCHK: 0x47, CF: 0
	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
	FC: 4915200 kHz
rx_jesd lane 1 status:
Errors: 0
	CGS state: DATA
	Initial Frame Synchronization: Yes
	Lane Latency: 1 Multi-frames and 62 Octets
	Initial Lane Alignment Sequence: Yes
	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
	K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
	FCHK: 0x48, CF: 0
	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
	FC: 4915200 kHz
tx_jesd status:
	Link is enabled
	Measured Link Clock: 122.882 MHz
	Reported Link Clock: 122.880 MHz
	Lane rate: 4915.200 MHz
	Lane rate / 40: 122.880 MHz
	LMFC rate: 7.680 MHz
	SYNC~: deasserted
	Link status: DATA
	SYSREF captured: Yes
	SYSREF alignment error: No
rx_os_jesd status:
	Link is enabled
	Measured Link Clock: 122.882 MHz
	Reported Link Clock: 122.880 MHz
	Lane rate: 4915.200 MHz
	Lane rate / 40: 122.880 MHz
	LMFC rate: 7.680 MHz
	Link status: DATA
	SYSREF captured: Yes
	SYSREF alignment error: No
rx_os_jesd lane 0 status:
Errors: 0
	CGS state: DATA
	Initial Frame Synchronization: Yes
	Lane Latency: 1 Multi-frames and 56 Octets
	Initial Lane Alignment Sequence: Yes
	DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
	FCHK: 0x43, CF: 0
	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
	FC: 4915200 kHz
rx_os_jesd lane 1 status:
Errors: 0
	CGS state: DATA
	Initial Frame Synchronization: Yes
	Lane Latency: 1 Multi-frames and 56 Octets
	Initial Lane Alignment Sequence: Yes
	DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
	K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
	FCHK: 0x44, CF: 0
	ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
	FC: 4915200 kHz
tx_dac: Successfully initialized (245761108 Hz)
rx_adc: Successfully initialized (122880554 Hz)
rx_obs_adc: Successfully initialized (245761108 Hz)
DMA_EXAMPLE: address=0x951c0 samples=65536 channels=4 bits=16
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