• Zynq中断与AMP~双核串口环回之PS与PL通信

    实现思路：

    1.通过PL实现定时器每隔特定的时间为CPU0和CPU1发送硬中断；

    2.注册Uart中断，使用超时中断事件，当发送指定命令的时候，CPU0会因为Uart中断停止硬中断，将发送的命令中指定的数据写入到缓存区A中，并且向CPU1发送软中断；

    3.CPU1收到来自CPU0的软中断，停止指向自身的硬中断，检查缓存区A中的指定数据，如果符合约定的命令，将缓存区A中的数据写入缓存区B，且向CPU0发送软中断；

    4.CPU0收到来自CPU1的软中断，将缓存区B的数据读出并且通过Uart完成发送；

    细节：

    这里的缓存区RAM可以通过创建IP直接创建，也可以通过IP核：

            Block Memory Generator

            进行创建，因为是GP口，地址和数据默认为 32 位。

    此外：对于AXI LITE缓存区主要是通过Xil提供的驱动实现的，但也可以输出给PL；

    实验现象：

    部分代码：

    其中读写Bram的代码可参考：

    Axi_Lite接口的IP核与地址与缓冲与AxiGP0-CSDN博客

    CPU0中配置的Uart中断回调函数

            设置的是超时中断触发，set阈值那个不太好用。

            检测收到的Uart数据，符合标准则发送软中断给CPU1，并且禁用硬中断；

    1. void Uart0_IntrHandler(void *CallBackRef, u32 Event, unsigned int EventData)
    2. {
    3. 	if (Event == XUARTPS_EVENT_RECV_TOUT) {
    4. 		TotalReceivedCount = EventData;
    5.         if (TotalReceivedCount == 8 
    6.         && RecvBuffer[0] == 0x55 && RecvBuffer[1] == 0x55
    7.         && RecvBuffer[2] == 0x00 && RecvBuffer[3] == 0x01)
    8.         {
    9.             XScuGic_Disable(&GIC_SGI_instance_point, Interrupt_ID_Hardware_1);
    10.             XScuGic_Disable(&GIC_SGI_instance_point, Interrupt_ID_Hardware_0);
    11.             Axi_WriteRamA(RecvBuffer,TotalReceivedCount);
    12.             printf("Close SPI\n\r");
    13.             XScuGic_SoftwareIntr(&GIC_SGI_instance_point,
    14.                                   Interrupt_ID_SGI_15,
    15.                                   XSCUGIC_SPI_CPU1_MASK);
    16.         }
    17.         else if(TotalReceivedCount == 8 && RecvBuffer[0] == 0x66)
    18.         {
    19.             XScuGic_Enable(&GIC_SGI_instance_point, Interrupt_ID_Hardware_0);
    20.             printf("Open SPI\n\r");
    21.         }
    22. 	}
    23. 	XUartPs_Recv(&Uart_Instance_point, RecvBuffer, TEST_BUFFER_SIZE);
    24. }

    CPU1的软中断回调函数

    检查缓存区A中的数据是否符合要求，如果符合要求则写入缓存区B，

    同时向CPU0发送软中断；

    1.  
    2. void SGI_IntrHandler(void *CallBackRef){
    3.     u32 origin_command;
    4. 	print("SG1!\n\r");
    5. 	Axi_ReadRamA(COMMAND_BUFFER,8);
    6.     if(COMMAND_BUFFER[4]==0x04 && COMMAND_BUFFER[5] == 0x05 
    7.     && COMMAND_BUFFER[6]==0x06 && COMMAND_BUFFER[7] == 0x07)
    8.         {
    9.             Axi_WriteRamB(COMMAND_BUFFER,8);
    10.             XScuGic_SoftwareIntr(&GIC_SGI_instance_point, Interrupt_ID_SGI_14, CPU_id_0);
    11.         }
    12. }

    CPU0的软中断回调函数

    将缓存区B中的数据用Uart发送；

    1. void SGI_IntrHandler(void *CallBackRef){
    2.       Axi_ReadRamB(SendBuffer,8);
    3.       XUartPs_Send(&Uart_Instance_point, SendBuffer, 8);
    4. 	  print("SG0!\n\r");
    5. }

    整体代码：

    1. /******************************************************************************
    2. *
    3. * Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
    4. *
    5. * Permission is hereby granted, free of charge, to any person obtaining a copy
    6. * of this software and associated documentation files (the "Software"), to deal
    7. * in the Software without restriction, including without limitation the rights
    8. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    9. * copies of the Software, and to permit persons to whom the Software is
    10. * furnished to do so, subject to the following conditions:
    11. *
    12. * The above copyright notice and this permission notice shall be included in
    13. * all copies or substantial portions of the Software.
    14. *
    15. * Use of the Software is limited solely to applications:
    16. * (a) running on a Xilinx device, or
    17. * (b) that interact with a Xilinx device through a bus or interconnect.
    18. *
    19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    22. * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
    23. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
    24. * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
    25. * SOFTWARE.
    26. *
    27. * Except as contained in this notice, the name of the Xilinx shall not be used
    28. * in advertising or otherwise to promote the sale, use or other dealings in
    29. * this Software without prior written authorization from Xilinx.
    30. *
    31. ******************************************************************************/
    32.  
    33. /*
    34.  * helloworld.c: simple test application
    35.  *
    36.  * This application configures UART 16550 to baud rate 9600.
    37.  * PS7 UART (Zynq) is not initialized by this application, since
    38.  * bootrom/bsp configures it to baud rate 115200
    39.  *
    40.  * ------------------------------------------------
    41.  * | UART TYPE   BAUD RATE                        |
    42.  * ------------------------------------------------
    43.  *   uartns550   9600
    44.  *   uartlite    Configurable only in HW design
    45.  *   ps7_uart    115200 (configured by bootrom/bsp)
    46.  */
    47.  
    48. #include 
    49. #include "platform.h"
    50. #include "xil_printf.h"
    51. #include "xil_mmu.h"
    52. #include "xscugic.h"
    53. #include "xuartps.h"
    54. #include "xparameters.h"
    55. #include "xil_exception.h"
    56. #include "Axi_REG_List.h"
    57.  
    58. #define COMM_VAL  (*(volatile unsigned long *)(0xFFFF0000))
    59. #define APP_CPU1_ADDR	0x02000000
    60. #define OCM_ADDR 0xFFFF0000
    61. #define Interrupt_ID_SGI_14 0x0D
    62. #define Interrupt_ID_SGI_15 0x0E
    63. #define Interrupt_ID_Hardware_0 61
    64. #define Interrupt_ID_Hardware_1 62
    65. #define DistBaseAddress XPAR_PS7_SCUGIC_0_DIST_BASEADDR
    66. //AXI BaseAddr
    67. #define Axi_RamA_BaseAddr 0x43C00000
    68. #define Axi_RamB_BaseAddr 0x43C10000
    69. //GIC
    70. #define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
    71. #define GIC_DECIVE_ID_INT    XPAR_SCUGIC_0_DEVICE_ID
    72. //CPU_ID
    73. #define CPU_id_0 XSCUGIC_SPI_CPU0_MASK
    74. #define CPU_id_1 XSCUGIC_SPI_CPU1_MASK
    75. //Uart
    76. #define Interrupt_ID_Uart_0 XPS_UART0_INT_ID
    77. #define Uart_Decive_ID XPAR_PS7_UART_0_DEVICE_ID
    78. static  XUartPs_Config *Uart_ConFig;
    79. static  XUartPs Uart_Instance_point;
    80. #define TEST_BUFFER_SIZE	32
    81. u8 SendBuffer[TEST_BUFFER_SIZE];	/* Buffer for Transmitting Data */ 
    82. u8 RecvBuffer[TEST_BUFFER_SIZE];	/* Buffer for Receiving Data */
    83. volatile int TotalReceivedCount;
    84. //SGI
    85. static XScuGic_Config *GIC_SGI_ConFig;
    86. static XScuGic         GIC_SGI_instance_point;
    87.  
    88.  
    89. int  Uart_init();
    90. int  GIC_SGI_init();
    91. void Uart_SetHandler_Event();
    92. void SGI_IntrHandler(void *CallBackRef);
    93. void Hardware_IntrHandler(void *CallBackRef);
    94. void Uart0_IntrHandler(void *CallBackRef, u32 Event, unsigned int EventData);
    95. void Axi_WriteRamA(u8 *Data_addr_point, u32 Write_ByteLong);
    96. void Axi_ReadRamB (u8 *Data_addr_point, u32 Read_ByteLong );
    97. int main()
    98. {
    99.     int Status;
    100.     COMM_VAL = 0;
    101.     Status = Uart_init();
    102.     if (Status != XST_SUCCESS) {
    103. 		return XST_FAILURE;
    104. 	}
    105.     Status = GIC_SGI_init();
    106.     if (Status != XST_SUCCESS) {
    107. 		return XST_FAILURE;
    108. 	}
    109. 	Xil_SetTlbAttributes(0xFFFF0000,0x14de2);
    110.     Uart_SetHandler_Event();
    111.     while(1){
    112.         print("CPU0: Hello World CPU 0\n\r");
    113. 		COMM_VAL = 1;
    114. 		while(COMM_VAL == 1){
    115. 		}
    116.     }
    117.     return 0;
    118. }
    119.  
    120. int GIC_SGI_init(){
    121.     int Status;
    122.  
    123.     Xil_ExceptionInit();
    124.     GIC_SGI_ConFig = XScuGic_LookupConfig(GIC_DECIVE_ID_INT);
    125. 	if (NULL == GIC_SGI_ConFig) {
    126. 		return XST_FAILURE;
    127. 	}
    128.  
    129. 	Status = XScuGic_CfgInitialize(&GIC_SGI_instance_point,
    130.                                     GIC_SGI_ConFig,
    131.                                     GIC_SGI_ConFig->CpuBaseAddress);
    132. 	if (Status != XST_SUCCESS) {
    133. 		return XST_FAILURE;
    134. 	}
    135.     Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
    136.                                 (Xil_ExceptionHandler) XScuGic_InterruptHandler,
    137.                                 &GIC_SGI_instance_point);
    138.     //---------------------------------------------------------------//
    139.     //SGI
    140.     Status = XScuGic_Connect(&GIC_SGI_instance_point,
    141.                     Interrupt_ID_SGI_14,
    142.                     (Xil_InterruptHandler )SGI_IntrHandler,
    143.                     (void *)&GIC_SGI_instance_point
    144.                     );
    145.     if (Status != XST_SUCCESS) {
    146. 		return XST_FAILURE;
    147. 	}
    148.     XScuGic_Enable(&GIC_SGI_instance_point,
    149.                     Interrupt_ID_SGI_14);
    150.     //SPI hardware----------------------------------------------------//
    151.     Status = XScuGic_Connect(&GIC_SGI_instance_point,
    152.                     Interrupt_ID_Hardware_0,
    153.                     (Xil_InterruptHandler )Hardware_IntrHandler,
    154.                     (void *)&GIC_SGI_instance_point
    155.                     );
    156.     if (Status != XST_SUCCESS) {
    157. 		return XST_FAILURE;
    158. 	}
    159.     XScuGic_SetPriTrigTypeByDistAddr(DistBaseAddress,
    160.                                      Interrupt_ID_Hardware_0,
    161.                                      0x20,
    162.                                      0x03);
    163.     XScuGic_InterruptMaptoCpu(&GIC_SGI_instance_point,
    164.                                 CPU_id_0,
    165. 								Interrupt_ID_Hardware_0);
    166.     XScuGic_Enable(&GIC_SGI_instance_point,
    167.                     Interrupt_ID_Hardware_0);
    168.     //Uart interrupt--------------------------------------------------//
    169.     Status = XScuGic_Connect(&GIC_SGI_instance_point,
    170.                     Interrupt_ID_Uart_0,
    171.                     (Xil_InterruptHandler )XUartPs_InterruptHandler,
    172.                     (void *)&Uart_Instance_point
    173.                     );
    174.     if (Status != XST_SUCCESS) {
    175. 		return XST_FAILURE;
    176. 	}
    177.     XScuGic_Enable(&GIC_SGI_instance_point, Interrupt_ID_Uart_0);
    178.     //---------------------------------------------------------------//
    179.     Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
    180.     return XST_SUCCESS;
    181. }
    182. int Uart_init(){
    183.     s32 Status = XST_SUCCESS;
    184.     Uart_ConFig = XUartPs_LookupConfig(Uart_Decive_ID);
    185.     if (NULL == Uart_ConFig) {
    186. 		return XST_FAILURE;
    187. 	}
    188.     Status = XUartPs_CfgInitialize(&Uart_Instance_point, 
    189.                                     Uart_ConFig, 
    190.                                     Uart_ConFig->BaseAddress);
    191.     if (Status != XST_SUCCESS) {
    192. 		return XST_FAILURE;
    193. 	}                   
    194.     Status = XUartPs_SelfTest(&Uart_Instance_point);
    195. 	if (Status != XST_SUCCESS) {
    196. 		return XST_FAILURE;
    197. 	}       
    198.     Status = XUartPs_SetBaudRate(&Uart_Instance_point,115200);    
    199.     if (Status != XST_SUCCESS) {
    200. 		return XST_FAILURE;
    201. 	}
    202.     return Status;
    203. }
    204.  
    205. void Uart_SetHandler_Event(){
    206.     u32 IntrMask = 0;
    207.     int Index;
    208.     XUartPs_SetHandler(&Uart_Instance_point,
    209.                       (XUartPs_Handler) Uart0_IntrHandler,
    210.                        &Uart_Instance_point);
    211. 	IntrMask = XUARTPS_IXR_TOUT|XUARTPS_IXR_RXOVR;
    212.     XUartPs_SetInterruptMask(&Uart_Instance_point, IntrMask);
    213.     XUartPs_SetOperMode(&Uart_Instance_point,XUARTPS_OPER_MODE_NORMAL);
    214.     XUartPs_SetRecvTimeout(&Uart_Instance_point,8);
    215.     // XUartPs_SetFifoThreshold(&Uart_Instance_point,8);
    216.     // Clear Buffer
    217.     for (Index = 0; Index < TEST_BUFFER_SIZE; Index++) {
    218. 		SendBuffer[Index] = 0;
    219. 		RecvBuffer[Index] = 0;
    220. 	}
    221.     XUartPs_Recv(&Uart_Instance_point, RecvBuffer, TEST_BUFFER_SIZE);
    222.     // XUartPs_Send(&Uart_Instance_point, SendBuffer, TEST_BUFFER_SIZE);
    223. }
    224. void SGI_IntrHandler(void *CallBackRef){
    225.       Axi_ReadRamB(SendBuffer,8);
    226.       XUartPs_Send(&Uart_Instance_point, SendBuffer, 8);
    227. 	  print("SG0!\n\r");
    228. }
    229. void Hardware_IntrHandler(void *CallBackRef){
    230. //    print("Hardware:CLOCK Interrupt CPU0!\n\r");
    231. 	  print("H0!\n\r");
    232. }
    233. /**************************************************************************/
    234. /**
    235. *
    236. * This function is the handler which performs processing to handle data events
    237. * from the device.  It is called from an interrupt context. so the amount of
    238. * processing should be minimal.
    239. *
    240. * This handler provides an example of how to handle data for the device and
    241. * is application specific.
    242. *
    243. * @param	CallBackRef contains a callback reference from the driver,
    244. *		in this case it is the instance pointer for the XUartPs driver.
    245. * @param	Event contains the specific kind of event that has occurred.
    246. * @param	EventData contains the number of bytes sent or received for sent
    247. *		and receive events.
    248. *
    249. * @return	None.
    250. *
    251. * @note		None.
    252. *
    253. ***************************************************************************/
    254. void Uart0_IntrHandler(void *CallBackRef, u32 Event, unsigned int EventData)
    255. {
    256. 	if (Event == XUARTPS_EVENT_RECV_TOUT) {
    257. 		TotalReceivedCount = EventData;
    258.         if (TotalReceivedCount == 8 
    259.         && RecvBuffer[0] == 0x55 && RecvBuffer[1] == 0x55
    260.         && RecvBuffer[2] == 0x00 && RecvBuffer[3] == 0x01)
    261.         {
    262.              XScuGic_Disable(&GIC_SGI_instance_point, Interrupt_ID_Hardware_1);
    263.              XScuGic_Disable(&GIC_SGI_instance_point, Interrupt_ID_Hardware_0);
    264.             Axi_WriteRamA(RecvBuffer,TotalReceivedCount);
    265.             printf("Close SPI\n\r");
    266.             XScuGic_SoftwareIntr(&GIC_SGI_instance_point,
    267.                                   Interrupt_ID_SGI_15,
    268.                                   XSCUGIC_SPI_CPU1_MASK);
    269.         }
    270.         else if(TotalReceivedCount == 8 && RecvBuffer[0] == 0x66)
    271.         {
    272.             XScuGic_Enable(&GIC_SGI_instance_point, Interrupt_ID_Hardware_0);
    273.             printf("Open SPI\n\r");
    274.         }
    275. 	}
    276. 	XUartPs_Recv(&Uart_Instance_point, RecvBuffer, TEST_BUFFER_SIZE);
    277. }
    278. void Axi_WriteRamA(u8 *Data_addr_point, u32 Write_ByteLong){
    279.     int i;
    280.     for ( i = 0; i < Write_ByteLong; i++)
    281.     {
    282.         AXI_REG_LIST_mWriteReg(Axi_RamA_BaseAddr,i*4 ,*(Data_addr_point  + i));
    283.     }
    284. }
    285. void Axi_ReadRamB(u8 *Data_addr_point, u32 Read_ByteLong){
    286.     int i;
    287.     u32 Read_Data_Origin;
    288.     for ( i = 0; i < Read_ByteLong; i++)
    289.     {
    290.         Read_Data_Origin = AXI_REG_LIST_mReadReg(Axi_RamB_BaseAddr, i*4);
    291.         *(Data_addr_point + i) = (u8) Read_Data_Origin;
    292.     }
    293. }
    1. /******************************************************************************
    2. *
    3. * Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
    4. *
    5. * Permission is hereby granted, free of charge, to any person obtaining a copy
    6. * of this software and associated documentation files (the "Software"), to deal
    7. * in the Software without restriction, including without limitation the rights
    8. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    9. * copies of the Software, and to permit persons to whom the Software is
    10. * furnished to do so, subject to the following conditions:
    11. *
    12. * The above copyright notice and this permission notice shall be included in
    13. * all copies or substantial portions of the Software.
    14. *
    15. * Use of the Software is limited solely to applications:
    16. * (a) running on a Xilinx device, or
    17. * (b) that interact with a Xilinx device through a bus or interconnect.
    18. *
    19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    22. * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
    23. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
    24. * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
    25. * SOFTWARE.
    26. *
    27. * Except as contained in this notice, the name of the Xilinx shall not be used
    28. * in advertising or otherwise to promote the sale, use or other dealings in
    29. * this Software without prior written authorization from Xilinx.
    30. *
    31. ******************************************************************************/
    32.  
    33. /*
    34.  * helloworld.c: simple test application
    35.  *
    36.  * This application configures UART 16550 to baud rate 9600.
    37.  * PS7 UART (Zynq) is not initialized by this application, since
    38.  * bootrom/bsp configures it to baud rate 115200
    39.  *
    40.  * ------------------------------------------------
    41.  * | UART TYPE   BAUD RATE                        |
    42.  * ------------------------------------------------
    43.  *   uartns550   9600
    44.  *   uartlite    Configurable only in HW design
    45.  *   ps7_uart    115200 (configured by bootrom/bsp)
    46.  */
    47.  
    48. #include 
    49. #include "platform.h"
    50. #include "xil_printf.h"
    51. #include "xil_mmu.h"
    52. #include "xscugic.h"
    53. #include "Axi_REG_List.h"
    54. #include "xuartps.h"
    55. #include "xparameters.h"
    56. #include "xil_exception.h"
    57.  
    58. #define COMM_VAL  (*(volatile unsigned long *)(0xFFFF0000))
    59. #define APP_CPU1_ADDR	0x02000000
    60. #define OCM_ADDR 0xFFFF0000
    61. #define Interrupt_ID_SGI_14 0x0D
    62. #define Interrupt_ID_SGI_15 0x0E
    63. #define Interrupt_ID_Hardware_0 61
    64. #define Interrupt_ID_Hardware_1 62
    65. #define DistBaseAddress XPAR_PS7_SCUGIC_0_DIST_BASEADDR
    66. #define CPU_id_0 XSCUGIC_SPI_CPU0_MASK
    67. #define CPU_id_1 XSCUGIC_SPI_CPU1_MASK
    68. //AXI BaseAddr
    69. #define Axi_RamA_BaseAddr 0x43C00000
    70. #define Axi_RamB_BaseAddr 0x43C10000
    71. //GIC
    72. #define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
    73. #define GIC_DECIVE_ID_INT    XPAR_SCUGIC_0_DEVICE_ID
    74.  
    75. #define TEST_BUFFER_SIZE	32
    76. u8 Media_Buffer[TEST_BUFFER_SIZE];
    77.  
    78. static XScuGic_Config *GIC_SGI_ConFig;
    79. static XScuGic         GIC_SGI_instance_point;
    80.  
    81. int GIC_SGI_init();
    82. void SGI_IntrHandler(void *CallBackRef);
    83. void Hardware_IntrHandler(void *CallBackRef);
    84. void Axi_ReadRamA (u8 *Data_addr_point, u32 Read_ByteLong );
    85. void Axi_WriteRamB(u8 *Data_addr_point, u32 Write_ByteLong);
    86.  
    87. int main()
    88. {
    89.     int Status;
    90. 	Xil_SetTlbAttributes(0xFFFF0000,0x14de2);
    91.     while(1){
    92. 		while(COMM_VAL == 1){
    93. 			print("CPU1: Hello World CPU 1\n\r");
    94. 		    Status = GIC_SGI_init();
    95. 		    if (Status != XST_SUCCESS) {
    96. 				return XST_FAILURE;
    97. 			}
    98.             while (1){
    99.             }
    100.         }
    101.     }
    102.     return 0;
    103. }
    104.  
    105. int GIC_SGI_init(){
    106.     int Status;
    107.  
    108.     Xil_ExceptionInit();
    109.     GIC_SGI_ConFig = XScuGic_LookupConfig(GIC_DECIVE_ID_INT);
    110. 	if (NULL == GIC_SGI_ConFig) {
    111. 		return XST_FAILURE;
    112. 	}
    113.  
    114. 	Status = XScuGic_CfgInitialize(&GIC_SGI_instance_point,
    115.                                     GIC_SGI_ConFig,
    116.                                     GIC_SGI_ConFig->CpuBaseAddress);
    117. 	if (Status != XST_SUCCESS) {
    118. 		return XST_FAILURE;
    119. 	}
    120.     Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
    121.                                 (Xil_ExceptionHandler) XScuGic_InterruptHandler,
    122.                                 &GIC_SGI_instance_point);
    123.  
    124.     Status = XScuGic_Connect(&GIC_SGI_instance_point,
    125.     						Interrupt_ID_SGI_15,
    126. 							(Xil_InterruptHandler )SGI_IntrHandler,
    127. 							(void *)&GIC_SGI_instance_point
    128.                     		);
    129.     if (Status != XST_SUCCESS) {
    130. 		return XST_FAILURE;
    131. 	}
    132.     XScuGic_Enable(&GIC_SGI_instance_point,
    133.     				Interrupt_ID_SGI_15);
    134.     //HGI
    135.     Status = XScuGic_Connect(&GIC_SGI_instance_point,
    136.     				Interrupt_ID_Hardware_1,
    137.                     (Xil_InterruptHandler )Hardware_IntrHandler,
    138.                     (void *)&GIC_SGI_instance_point
    139.                     );
    140.     if (Status != XST_SUCCESS) {
    141. 		return XST_FAILURE;
    142. 	}
    143.     XScuGic_SetPriTrigTypeByDistAddr(DistBaseAddress,
    144.                                      Interrupt_ID_Hardware_1,
    145.                                      0x21,
    146.                                      0x03);
    147.     XScuGic_InterruptMaptoCpu(&GIC_SGI_instance_point,
    148.     							XSCUGIC_SPI_CPU1_MASK,
    149. 								Interrupt_ID_Hardware_1);
    150.     XScuGic_Enable(&GIC_SGI_instance_point,
    151.     		Interrupt_ID_Hardware_1);
    152.     Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
    153.     return XST_SUCCESS;
    154. }
    155.  
    156. void SGI_IntrHandler(void *CallBackRef){
    157.     u32 origin_command;
    158. 	print("SG1!\n\r");
    159. 	Axi_ReadRamA(Media_Buffer,8);
    160.     if(Media_Buffer[4]==0x04 && Media_Buffer[5] == 0x05 
    161.     && Media_Buffer[6]==0x06 && Media_Buffer[7] == 0x07)
    162.         {
    163.             Axi_WriteRamB(Media_Buffer,8);
    164.             XScuGic_SoftwareIntr(&GIC_SGI_instance_point, Interrupt_ID_SGI_14, CPU_id_0);
    165.         }
    166. }   
    167. void Hardware_IntrHandler(void *CallBackRef){
    168. 	  print("H1!\n\r");
    169. }
    170. void Axi_ReadRamA(u8 *Data_addr_point, u32 Read_ByteLong){
    171.     int i;
    172.     u32 Read_Data_Origin;
    173.     for ( i = 0; i < Read_ByteLong; i++)
    174.     {
    175.         Read_Data_Origin = AXI_REG_LIST_mReadReg(Axi_RamA_BaseAddr, i*4);
    176.         *(Data_addr_point + i) = (u8) Read_Data_Origin;
    177.     }
    178. }
    179. void Axi_WriteRamB(u8 *Data_addr_point, u32 Write_ByteLong){
    180.     int i;
    181.     for ( i = 0; i < Write_ByteLong; i++)
    182.     {
    183.         AXI_REG_LIST_mWriteReg(Axi_RamB_BaseAddr,i*4 ,*(Data_addr_point  + i));
    184.     }
    185. }

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  • 原文地址：https://blog.csdn.net/NoNoUnknow/article/details/133934875