• BL808学习日志-1-三核通讯

    接上个博客，今天实验了一下BL808的IPC通讯，使用的是博流自己的SDK；参考手册上并没有说明各个寄存器，是通过网友的结论和自己的部分修改达成的。

    一、实验代码

    1.目前仅测试了LP内核和M0内核之间的通讯，使用SIPEED的M1S_Dock开发板，修改了\bouffalo_sdk\bsp\board\bl808dk\board.c文件，先将debug的管脚14 15分配给M0内核使用，方便打印M0内核的日志；

    1. static void console_init()
    2. {
    3.     struct bflb_device_s *gpio;
    4.  
    5.     gpio = bflb_device_get_by_name("gpio");
    6. #if defined(CPU_M0)
    7.     bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX);
    8.     bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX);
    9. #elif defined(CPU_D0)
    10.     /* sipeed m1s dock */
    11.     bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
    12.     bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
    13. #elif defined(CPU_LP)
    14.     /* map GPIO_PIN_18 and GPIO_PIN_19 as UART for LP core */
    15.     bflb_gpio_uart_init(gpio, GPIO_PIN_18, GPIO_UART_FUNC_UART1_TX);
    16.     bflb_gpio_uart_init(gpio, GPIO_PIN_19, GPIO_UART_FUNC_UART1_RX);
    17. #endif
    18.     struct bflb_uart_config_s cfg;
    19.     cfg.baudrate = 2000000;
    20.     cfg.data_bits = UART_DATA_BITS_8;
    21.     cfg.stop_bits = UART_STOP_BITS_1;
    22.     cfg.parity = UART_PARITY_NONE;
    23.     cfg.flow_ctrl = 0;
    24.     cfg.tx_fifo_threshold = 7;
    25.     cfg.rx_fifo_threshold = 7;
    26. #if defined(CPU_M0)
    27.     uart0 = bflb_device_get_by_name("uart0");
    28. #elif defined(CPU_D0)
    29.     uart0 = bflb_device_get_by_name("uart3");
    30. #elif defined(CPU_LP)
    31.     uart0 = bflb_device_get_by_name("uart1");
    32. #endif
    33.     bflb_uart_init(uart0, &cfg);
    34.     bflb_uart_set_console(uart0);
    35. }

    2.在bouffalo_sdk\examples\bl808_triplecore\helloworld_m0例程上进行修改，M0主函数中对中断寄存器进行了初始化，定义了中断回调函数；并在中断函数中输出IPC中断号；其中对LED灯进行了一个0.5Hz的闪烁，来提示系统进行了正常的IPC通讯。

    1. #include "bflb_mtimer.h"
    2. #include "board.h"
    3. #include "bflb_gpio.h"
    4. #include "bl808.h"
    5. #include "ipc_reg.h"
    6. #include "bl808_ipc.h"
    7. #include "bl808_common.h"
    8.  
    9. #define DBG_TAG "M0"
    10. #include "log.h"
    11.  
    12. struct bflb_device_s *gpio;
    13. uint32_t value = 0;
    14. void IPC_M0_IRQHandler(void)
    15. {
    16. 	gpio = bflb_device_get_by_name("gpio");
    17. 	// Read Interrupt Status
    18. 	uint32_t irqStatus = BL_RD_REG(IPC0_BASE, IPC_CPU0_IPC_IRSRR);
    19.  
    20. 	//Interrupt handle
    21. 	bflb_gpio_set(gpio,GPIO_PIN_8);
    22. 	 LOG_F("the irqStatus value is %d\r\n",irqStatus);
    23. 	value = 1;
    24. 	//Clear Interrypt
    25. 	BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, irqStatus);
    26. }
    27.  
    28. void m0_ipc_init(void)
    29. {
    30. 	/* setup the IPC Interupt */
    31. 	bflb_irq_attach(IPC_M0_IRQn, IPC_M0_IRQHandler, NULL);
    32. 	BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, 1 << 1);
    33. 	bflb_irq_enable(IPC_M0_IRQn);
    34. }
    35.  
    36.  
    37. int main(void)
    38. {
    39.     board_init();
    40.     m0_ipc_init();
    41.     while (1) {
    42.         if(value == 1)
    43.         {
    44.         	bflb_gpio_set(gpio,GPIO_PIN_8);
    45.         	bflb_mtimer_delay_ms(1000);
    46.         	bflb_gpio_reset(gpio,GPIO_PIN_8);
    47.             LOG_F("hello world m0\r\n");
    48.             LOG_E("hello world m0\r\n");
    49.             LOG_W("hello world m0\r\n");
    50.             LOG_I("hello world m0\r\n");
    51.             LOG_D("hello world m0\r\n");
    52.             LOG_T("hello world m0\r\n");
    53.  
    54.         }
    55.         bflb_mtimer_delay_ms(1000);
    56.  
    57.     }
    58.  
    59. }

    将M0程序烧录到开发板中；

    2.在bouffalo_sdk\examples\bl808_triplecore\helloworld_lp将LP板载外设初始化，然后打开开发板上的LED灯，使用IO8控制；默认上电拉低IO8，打开闪光灯；进入主循环之前，使能M0内核的IPC通道1；

    1. #include "bflb_mtimer.h"
    2. #include "board.h"
    3. #include "bflb_gpio.h"
    4. #include "bl808.h"
    5. #include "ipc_reg.h"
    6. #include "bl808_common.h"
    7.  
    8. #define DBG_TAG "MAIN"
    9. #include "log.h"
    10. struct bflb_device_s *gpio;
    11.  
    12.  
    13.  
    14. int main(void)
    15. {
    16.  
    17.     board_init();
    18.     gpio = bflb_device_get_by_name("gpio");
    19.     bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_OUTPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0);
    20.     bflb_gpio_reset(gpio,GPIO_PIN_8);
    21.  
    22.  
    23.     LOG_F("hello world lp\r\n");
    24.     LOG_E("hello world lp\r\n");
    25.     LOG_W("hello world lp\r\n");
    26.     LOG_I("hello world lp\r\n");
    27.     LOG_D("hello world lp\r\n");
    28.     LOG_T("hello world lp\r\n");
    29.     LOG_I("LPcore will comunity to M0 core");
    30.     BL_WR_REG(IPC0_BASE, IPC_CPU1_IPC_ISWR, 1 << 1);
    31.  
    32.     while (1) {
    33.  
    34.         bflb_mtimer_delay_ms(1000);
    35.     }
    36. }

     将LP内核程序烧录到开发板中，会看到LED灯先是亮起，然后被M0主程序改为1秒闪烁1次；

    3.若是想看debug日志，默认是查看M0内核的日志，可以把board.c文件中LP和M0的串口引脚对换。输出的LP内核的日志：

    1.   ____               __  __      _       _       _
    2.  |  _ \             / _|/ _|    | |     | |     | |
    3.  | |_) | ___  _   _| |_| |_ __ _| | ___ | | __ _| |__
    4.  |  _ < / _ \| | | |  _|  _/ _` | |/ _ \| |/ _` | '_ \
    5.  | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |
    6.  |____/ \___/ \__,_|_| |_| \__,_|_|\___/|_|\__,_|_.__/
    7.  
    8. Build:18:11:43,Oct  1 2023
    9. Copyright (c) 2022 Bouffalolab team
    10. lp does not use memheap due to little ram
    11. sig1:ffff76ff
    12. sig2:0000ffff
    13. cgen1:9f7ffffd
    14. [F][LP] hello world lp
    15. [E][LP] hello world lp
    16. [W][LP] hello world lp
    17. [I][LP] hello world lp
    18. [I][LP] LPcore will comunity to M0 core

    4.输出的M0内核日志：

    1.  
    2.   ____               __  __      _       _       _
    3.  |  _ \             / _|/ _|    | |     | |     | |
    4.  | |_) | ___  _   _| |_| |_ __ _| | ___ | | __ _| |__
    5.  |  _ < / _ \| | | |  _|  _/ _` | |/ _ \| |/ _` | '_ \
    6.  | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |
    7.  |____/ \___/ \__,_|_| |_| \__,_|_|\___/|_|\__,_|_.__/
    8.  
    9. Build:18:21:31,Oct  1 2023
    10. Copyright (c) 2022 Bouffalolab team
    11. ======== flash cfg ========
    12. flash size 0x01000000
    13. jedec id     0xEF4018
    14. mid              0xEF
    15. iomode           0x04
    16. clk delay        0x01
    17. clk invert       0x01
    18. read reg cmd0    0x05
    19. read reg cmd1    0x35
    20. write reg cmd0   0x01
    21. write reg cmd1   0x31
    22. qe write len     0x01
    23. cread support    0x00
    24. cread code       0xFF
    25. burst wrap cmd   0x77
    26. ===========================
    27. dynamic memory init success,heap size = 21 Kbyte
    28. sig1:ffff32ff
    29. sig2:0000ffff
    30. [F][M0] the irqStatus value is 2
    31. [F][M0] hello world m0
    32. [E][M0] hello world m0

    可以看到，M0日志显示"the irqSstatus value is 2"，也就是通道1触发； 

    4.随机试验了一下其他的通道，试验通道0能否正常触发，修改LP内核main.c文件的触发为

    1. int main(void)
    2. {
    3.  
    4.     board_init();
    5.     gpio = bflb_device_get_by_name("gpio");
    6.     bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_OUTPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0);
    7.     bflb_gpio_reset(gpio,GPIO_PIN_8);
    8.  
    9.     LOG_F("hello world lp\r\n");
    10.     LOG_E("hello world lp\r\n");
    11.     LOG_W("hello world lp\r\n");
    12.     LOG_I("hello world lp\r\n");
    13.     LOG_D("hello world lp\r\n");
    14.     LOG_T("hello world lp\r\n");
    15.     LOG_I("LPcore will comunity to M0 core");
    16.     BL_WR_REG(IPC0_BASE, IPC_CPU1_IPC_ISWR, 1 << 0);
    17.  
    18.     while (1) {
    19.  
    20.         bflb_mtimer_delay_ms(1000);
    21.     }
    22. }

    修改M0内核中main.c文件中的使能通道

    1. void m0_ipc_init(void)
    2. {
    3. 	/* setup the IPC Interupt */
    4. 	bflb_irq_attach(IPC_M0_IRQn, IPC_M0_IRQHandler, NULL);
    5. 	BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, 1 << 0);
    6. 	bflb_irq_enable(IPC_M0_IRQn);
    7. }
    8.

     编译烧录到开发板，发现M0内核的输出日志发生变化为"the irqSstatus value is 1"，也就是通道0触发； 

    1.  
    2.   ____               __  __      _       _       _
    3.  |  _ \             / _|/ _|    | |     | |     | |
    4.  | |_) | ___  _   _| |_| |_ __ _| | ___ | | __ _| |__
    5.  |  _ < / _ \| | | |  _|  _/ _` | |/ _ \| |/ _` | '_ \
    6.  | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |
    7.  |____/ \___/ \__,_|_| |_| \__,_|_|\___/|_|\__,_|_.__/
    8.  
    9. Build:18:21:31,Oct  1 2023
    10. Copyright (c) 2022 Bouffalolab team
    11. ======== flash cfg ========
    12. flash size 0x01000000
    13. jedec id     0xEF4018
    14. mid              0xEF
    15. iomode           0x04
    16. clk delay        0x01
    17. clk invert       0x01
    18. read reg cmd0    0x05
    19. read reg cmd1    0x35
    20. write reg cmd0   0x01
    21. write reg cmd1   0x31
    22. qe write len     0x01
    23. cread support    0x00
    24. cread code       0xFF
    25. burst wrap cmd   0x77
    26. ===========================
    27. dynamic memory init success,heap size = 21 Kbyte
    28. sig1:ffff32ff
    29. sig2:0000ffff
    30. [F][M0] the irqStatus value is 1
    31. [F][M0] hello world m0
    32. [E][M0] hello world m0

    二、SIPEED默认库IPC描述

    SIPEED的默认M1S_BL808_SDK中对IPC和XRAM进行了更深层次的封装，也实现了XRAM的数据交互，包括bl808_ipc.c文件，其中XRAM是作为一个组件使用，封装的相当好，这里也是很不明白为什么博流自己的SDK却删掉了这部分的内容。贴个代码，应该就知道怎么使用了。

    1. /*
    2.  * Copyright (c) 2020 Bouffalolab.
    3.  *
    4.  * This file is part of
    5.  *     *** Bouffalolab Software Dev Kit ***
    6.  *      (see www.bouffalolab.com).
    7.  *
    8.  * Redistribution and use in source and binary forms, with or without modification,
    9.  * are permitted provided that the following conditions are met:
    10.  *   1. Redistributions of source code must retain the above copyright notice,
    11.  *      this list of conditions and the following disclaimer.
    12.  *   2. Redistributions in binary form must reproduce the above copyright notice,
    13.  *      this list of conditions and the following disclaimer in the documentation
    14.  *      and/or other materials provided with the distribution.
    15.  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
    16.  *      may be used to endorse or promote products derived from this software
    17.  *      without specific prior written permission.
    18.  *
    19.  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    20.  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    21.  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
    22.  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
    23.  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
    24.  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
    25.  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
    26.  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
    27.  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    28.  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    29.  */
    31. #include "bl808_ipc.h"
    32.  
    33. /** @addtogroup  BL606P_Peripheral_Driver
    34.  *  @{
    35.  */
    37. /** @addtogroup  IPC
    38.  *  @{
    39.  */
    41. /** @defgroup  IPC_Private_Macros
    42.  *  @{
    43.  */
    44. #define IPC_LP_OFFSET_IN_M0 0
    45. #define IPC_D0_OFFSET_IN_M0 16
    46.  
    47. #define IPC_M0_OFFSET_IN_LP 0
    48. #define IPC_D0_OFFSET_IN_LP 16
    49.  
    50. #define IPC_M0_OFFSET_IN_D0 0
    51. #define IPC_LP_OFFSET_IN_D0 16
    52.  
    53. /*@} end of group IPC_Private_Macros */
    54.  
    55. /** @defgroup  IPC_Private_Types
    56.  *  @{
    57.  */
    59. /*@} end of group IPC_Private_Types */
    60.  
    61. /** @defgroup  IPC_Private_Variables
    62.  *  @{
    63.  */
    65. ipcIntCallback *m0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };
    66. ipcIntCallback *lpIpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };
    67. ipcIntCallback *d0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL };
    68.  
    69. /*@} end of group IPC_Private_Variables */
    70.  
    71. /** @defgroup  IPC_Global_Variables
    72.  *  @{
    73.  */
    75. /*@} end of group IPC_Global_Variables */
    76.  
    77. /** @defgroup  IPC_Private_Fun_Declaration
    78.  *  @{
    79.  */
    81. /*@} end of group IPC_Private_Fun_Declaration */
    82.  
    83. /** @defgroup  IPC_Private_Functions
    84.  *  @{
    85.  */
    87. /*@} end of group IPC_Private_Functions */
    88.  
    89. /** @defgroup  IPC_Public_Functions
    90.  *  @{
    91.  */
    92. #if defined(CPU_M0) || defined(CPU_LP)
    93. /****************************************************************************/ /**
    94.  * @brief  M0 IPC interrupt init
    95.  *
    96.  * @param  onLPTriggerCallBack: Callback when LP trigger
    97.  *
    98.  * @param  onD0TriggerCallBack: Callback when D0 trigger
    99.  *
    100.  * @return None
    101.  *
    102. *******************************************************************************/
    103. void IPC_M0_Init(ipcIntCallback *onLPTriggerCallBack,
    104.                  ipcIntCallback *onD0TriggerCallBack)
    105. {
    106.     m0IpcIntCbfArra[0] = onLPTriggerCallBack;
    107.     m0IpcIntCbfArra[1] = onD0TriggerCallBack;
    108.  
    109.     IPC_M0_Int_Unmask_By_Word(0xffffffff);
    110.  
    111. #ifndef BFLB_USE_HAL_DRIVER
    112.     Interrupt_Handler_Register(IPC_M0_IRQn, IPC_M0_IRQHandler);
    113. #endif
    114.     CPU_Interrupt_Enable(IPC_M0_IRQn);
    115. }
    116. #endif
    117.  
    118. /****************************************************************************/ /**
    119.  * @brief  M0 unmask IPC interrupt
    120.  *
    121.  * @param  src: M0 IPC interrupt source
    122.  *
    123.  * @return None
    124.  *
    125. *******************************************************************************/
    126. void IPC_M0_Int_Unmask(IPC_Int_Src_Type src)
    127. {
    128.     uint32_t tmpVal = 0;
    129.  
    130.     /* Check the parameters */
    131.     CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
    132.  
    133.     tmpVal = (1 << src);
    134.  
    135.     BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, tmpVal);
    136. }
    137.  
    138. /****************************************************************************/ /**
    139.  * @brief  M0 unmask IPC interrupt by word
    140.  *
    141.  * @param  src: IPC interrupt source in word,every bit is interrupt source
    142.  *
    143.  * @return None
    144.  *
    145. *******************************************************************************/
    146. void IPC_M0_Int_Unmask_By_Word(uint32_t src)
    147. {
    148.     BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, src);
    149. }
    150.  
    151. /****************************************************************************/ /**
    152.  * @brief  M0 get IPC interrupt raw status
    153.  *
    154.  * @param  None
    155.  *
    156.  * @return IPC interrupt raw status
    157.  *
    158. *******************************************************************************/
    159. uint32_t IPC_M0_Get_Int_Raw_Status(void)
    160. {
    161.     return BL_RD_REG(IPC0_BASE, IPC_CPU0_IPC_IRSRR);
    162. }
    163.  
    164. /****************************************************************************/ /**
    165.  * @brief  M0 clear IPC interrupt
    166.  *
    167.  * @param  src: M0 IPC interrupt source
    168.  *
    169.  * @return None
    170.  *
    171. *******************************************************************************/
    172. void IPC_M0_Clear_Int(IPC_Int_Src_Type src)
    173. {
    174.     uint32_t tmpVal = 0;
    175.  
    176.     /* Check the parameters */
    177.     CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
    178.  
    179.     tmpVal = (1 << src);
    180.  
    181.     BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, tmpVal);
    182. }
    183.  
    184. /****************************************************************************/ /**
    185.  * @brief  M0 clear IPC interrupt by word
    186.  *
    187.  * @param  src: IPC interrupt source in word,every bit is interrupt source
    188.  *
    189.  * @return None
    190.  *
    191. *******************************************************************************/
    192. void IPC_M0_Clear_Int_By_Word(uint32_t src)
    193. {
    194.     BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, src);
    195. }
    196.  
    197. /****************************************************************************/ /**
    198.  * @brief  CPUx trigger IPC interrupt to M0
    199.  *
    200.  * @param  src: IPC interrupt source
    201.  * 
    202.  * @param  cpuxOffset: CPU interrupt offset
    203.  *
    204.  * @return None
    205.  *
    206. *******************************************************************************/
    207. void IPC_CPUx_Trigger_M0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)
    208. {
    209.     uint32_t tmpVal = 0;
    210.  
    211.     /* Check the parameters */
    212.     //CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));
    213.  
    214.     tmpVal = (1 << (src + cpuxOffset));
    215.  
    216.     BL_WR_REG(IPC0_BASE, IPC_CPU1_IPC_ISWR, tmpVal);
    217. }
    218.  
    219. /****************************************************************************/ /**
    220.  * @brief  LP trigger IPC interrupt to M0
    221.  *
    222.  * @param  src: LP IPC interrupt source
    223.  *
    224.  * @return None
    225.  *
    226. *******************************************************************************/
    227. void IPC_LP_Trigger_M0(IPC_Grp_Int_Src_Type src)
    228. {
    229.     IPC_CPUx_Trigger_M0(src, IPC_LP_OFFSET_IN_M0);
    230. }
    231.  
    232. /****************************************************************************/ /**
    233.  * @brief  D0 trigger IPC interrupt to M0
    234.  *
    235.  * @param  src: D0 IPC interrupt source
    236.  *
    237.  * @return None
    238.  *
    239. *******************************************************************************/
    240. void IPC_D0_Trigger_M0(IPC_Grp_Int_Src_Type src)
    241. {
    242.     IPC_CPUx_Trigger_M0(src, IPC_D0_OFFSET_IN_M0);
    243. }
    244.  
    245. #if defined(CPU_M0) || defined(CPU_LP)
    246. /****************************************************************************/ /**
    247.  * @brief  LP IPC interrupt init
    248.  *
    249.  * @param  onM0TriggerCallBack: Callback when M0 trigger
    250.  *
    251.  * @param  onD0TriggerCallBack: Callback when D0 trigger
    252.  *
    253.  * @return None
    254.  *
    255. *******************************************************************************/
    256. void IPC_LP_Init(ipcIntCallback *onM0TriggerCallBack,
    257.                  ipcIntCallback *onD0TriggerCallBack)
    258. {
    259.     lpIpcIntCbfArra[0] = onM0TriggerCallBack;
    260.     lpIpcIntCbfArra[1] = onD0TriggerCallBack;
    261.  
    262.     IPC_LP_Int_Unmask_By_Word(0xffffffff);
    263.  
    264. #ifndef BFLB_USE_HAL_DRIVER
    265.     Interrupt_Handler_Register(IPC_LP_IRQn, IPC_LP_IRQHandler);
    266. #endif
    267.     CPU_Interrupt_Enable(IPC_LP_IRQn);
    268. }
    269. #endif
    270.  
    271. /****************************************************************************/ /**
    272.  * @brief  LP unmask IPC interrupt
    273.  *
    274.  * @param  src: LP IPC interrupt source
    275.  *
    276.  * @return None
    277.  *
    278. *******************************************************************************/
    279. void IPC_LP_Int_Unmask(IPC_Int_Src_Type src)
    280. {
    281.     uint32_t tmpVal = 0;
    282.  
    283.     /* Check the parameters */
    284.     CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
    285.  
    286.     tmpVal = (1 << src);
    287.  
    288.     BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, tmpVal);
    289. }
    290.  
    291. /****************************************************************************/ /**
    292.  * @brief  LP unmask IPC interrupt by word
    293.  *
    294.  * @param  src: IPC interrupt source in word,every bit is interrupt source
    295.  *
    296.  * @return None
    297.  *
    298. *******************************************************************************/
    299. void IPC_LP_Int_Unmask_By_Word(uint32_t src)
    300. {
    301.     BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, src);
    302. }
    303.  
    304. /****************************************************************************/ /**
    305.  * @brief  LP get IPC interrupt raw status
    306.  *
    307.  * @param  None
    308.  *
    309.  * @return IPC interrupt raw status
    310.  *
    311. *******************************************************************************/
    312. uint32_t IPC_LP_Get_Int_Raw_Status(void)
    313. {
    314.     return BL_RD_REG(IPC1_BASE, IPC_CPU0_IPC_IRSRR);
    315. }
    316.  
    317. /****************************************************************************/ /**
    318.  * @brief  LP clear IPC interrupt
    319.  *
    320.  * @param  src: LP IPC interrupt source
    321.  *
    322.  * @return None
    323.  *
    324. *******************************************************************************/
    325. void IPC_LP_Clear_Int(IPC_Int_Src_Type src)
    326. {
    327.     uint32_t tmpVal = 0;
    328.  
    329.     /* Check the parameters */
    330.     CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
    331.  
    332.     tmpVal = (1 << src);
    333.  
    334.     BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, tmpVal);
    335. }
    336.  
    337. /****************************************************************************/ /**
    338.  * @brief  LP clear IPC interrupt by word
    339.  *
    340.  * @param  src: IPC interrupt source in word,every bit is interrupt source
    341.  *
    342.  * @return None
    343.  *
    344. *******************************************************************************/
    345. void IPC_LP_Clear_Int_By_Word(uint32_t src)
    346. {
    347.     BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, src);
    348. }
    349.  
    350. /****************************************************************************/ /**
    351.  * @brief  CPUx trigger IPC interrupt to LP
    352.  *
    353.  * @param  src: IPC interrupt source
    354.  *
    355.  * @param  cpuxOffset: CPU interrupt offset
    356.  *
    357.  * @return None
    358.  *
    359. *******************************************************************************/
    360. void IPC_CPUx_Trigger_LP(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)
    361. {
    362.     uint32_t tmpVal = 0;
    363.  
    364.     /* Check the parameters */
    365.     //CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));
    366.  
    367.     tmpVal = (1 << (src + cpuxOffset));
    368.  
    369.     BL_WR_REG(IPC1_BASE, IPC_CPU1_IPC_ISWR, tmpVal);
    370. }
    371.  
    372. /****************************************************************************/ /**
    373.  * @brief  M0 trigger IPC interrupt to LP
    374.  *
    375.  * @param  src: M0 IPC interrupt source
    376.  *
    377.  * @return None
    378.  *
    379. *******************************************************************************/
    380. void IPC_M0_Trigger_LP(IPC_Grp_nIt_Src_Type src)
    381. {
    382.     IPC_CPUx_Trigger_LP(src, IPC_M0_OFFSET_IN_LP);
    383. }
    384.  
    385. /****************************************************************************/ /**
    386.  * @brief  D0 trigger IPC interrupt to LP
    387.  *
    388.  * @param  src: D0 IPC interrupt source
    389.  *
    390.  * @return None
    391.  *
    392. *******************************************************************************/
    393. void IPC_D0_Trigger_LP(IPC_Grp_Int_Src_Type src)
    394. {
    395.     IPC_CPUx_Trigger_LP(src, IPC_D0_OFFSET_IN_LP);
    396. }
    397.  
    398. #if defined(CPU_D0) || defined(CPU_D1)
    399. /****************************************************************************/ /**
    400.  * @brief  D0 IPC interrupt init
    401.  *
    402.  * @param  onM0TriggerCallBack: Callback when M0 trigger
    403.  *
    404.  * @param  onLPTriggerCallBack: Callback when LP trigger
    405.  *
    406.  * @return None
    407.  *
    408. *******************************************************************************/
    409. void IPC_D0_Init(ipcIntCallback *onM0TriggerCallBack,
    410.                  ipcIntCallback *onLPTriggerCallBack)
    411. {
    412.     d0IpcIntCbfArra[0] = onM0TriggerCallBack;
    413.     d0IpcIntCbfArra[1] = onLPTriggerCallBack;
    414.  
    415.     IPC_D0_Int_Unmask_By_Word(0xffffffff);
    416.  
    417. #ifndef BFLB_USE_HAL_DRIVER
    418.     Interrupt_Handler_Register(IPC_D0_IRQn, IPC_D0_IRQHandler);
    419. #endif
    420.     CPU_Interrupt_Enable(IPC_D0_IRQn);
    421. }
    422. #endif
    423.  
    424. /****************************************************************************/ /**
    425.  * @brief  D0 unmask IPC interrupt
    426.  *
    427.  * @param  src: D0 IPC interrupt source
    428.  *
    429.  * @return None
    430.  *
    431. *******************************************************************************/
    432. void IPC_D0_Int_Unmask(IPC_Int_Src_Type src)
    433. {
    434.     uint32_t tmpVal = 0;
    435.  
    436.     /* Check the parameters */
    437.     CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
    438.  
    439.     tmpVal = (1 << src);
    440.  
    441.     BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, tmpVal);
    442. }
    443.  
    444. /****************************************************************************/ /**
    445.  * @brief  D0 unmask IPC interrupt by word
    446.  *
    447.  * @param  src: D0 IPC interrupt source
    448.  *
    449.  * @return None
    450.  *
    451. *******************************************************************************/
    452. void IPC_D0_Int_Unmask_By_Word(uint32_t src)
    453. {
    454.     BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, src);
    455. }
    456.  
    457. /****************************************************************************/ /**
    458.  * @brief  D0 get IPC interrupt raw status
    459.  *
    460.  * @param  None
    461.  *
    462.  * @return IPC interrupt raw status
    463.  *
    464. *******************************************************************************/
    465. uint32_t IPC_D0_Get_Int_Raw_Status(void)
    466. {
    467.     return BL_RD_REG(IPC2_BASE, IPC_CPU0_IPC_IRSRR);
    468. }
    469.  
    470. /****************************************************************************/ /**
    471.  * @brief  D0 clear IPC interrupt
    472.  *
    473.  * @param  src: D0 IPC interrupt source
    474.  *
    475.  * @return None
    476.  *
    477. *******************************************************************************/
    478. void IPC_D0_Clear_Int(IPC_Int_Src_Type src)
    479. {
    480.     uint32_t tmpVal = 0;
    481.  
    482.     /* Check the parameters */
    483.     CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src));
    484.  
    485.     tmpVal = (1 << src);
    486.  
    487.     BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, tmpVal);
    488. }
    489.  
    490. /****************************************************************************/ /**
    491.  * @brief  D0 clear IPC interrupt by word
    492.  *
    493.  * @param  src: IPC interrupt source in word,every bit is interrupt source
    494.  *
    495.  * @return None
    496.  *
    497. *******************************************************************************/
    498. void IPC_D0_Clear_Int_By_Word(uint32_t src)
    499. {
    500.     BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, src);
    501. }
    502.  
    503. /****************************************************************************/ /**
    504.  * @brief  CPUx trigger IPC interrupt to D0
    505.  *
    506.  * @param  src: IPC interrupt source
    507.  *
    508.  * @param  cpuxOffset: CPU interrupt offset
    509.  *
    510.  * @return None
    511.  *
    512. *******************************************************************************/
    513. void IPC_CPUx_Trigger_D0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset)
    514. {
    515.     uint32_t tmpVal = 0;
    516.  
    517.     /* Check the parameters */
    518.     //CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src));
    519.  
    520.     tmpVal = (1 << (src + cpuxOffset));
    521.  
    522.     BL_WR_REG(IPC2_BASE, IPC_CPU1_IPC_ISWR, tmpVal);
    523. }
    524.  
    525. /****************************************************************************/ /**
    526.  * @brief  M0 trigger IPC interrupt to D0
    527.  *
    528.  * @param  src: M0 IPC interrupt source
    529.  *
    530.  * @return None
    531.  *
    532. *******************************************************************************/
    533. void IPC_M0_Trigger_D0(IPC_Grp_Int_Src_Type src)
    534. {
    535.     IPC_CPUx_Trigger_D0(src, IPC_M0_OFFSET_IN_D0);
    536. }
    537.  
    538. /****************************************************************************/ /**
    539.  * @brief  LP trigger IPC interrupt to D0
    540.  *
    541.  * @param  src: LP IPC interrupt source
    542.  *
    543.  * @return None
    544.  *
    545. *******************************************************************************/
    546. void IPC_LP_Trigger_D0(IPC_Grp_Int_Src_Type src)
    547. {
    548.     IPC_CPUx_Trigger_D0(src, IPC_LP_OFFSET_IN_D0);
    549. }
    550.  
    551. /****************************************************************************/ /**
    552.  * @brief  M0 trigger IPC interrupt to CPUx
    553.  *
    554.  * @param  tgtCPU: Target CPU
    555.  *
    556.  * @param  src: IPC interrupt source
    557.  *
    558.  * @return None
    559.  *
    560. *******************************************************************************/
    561. void IPC_M0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
    562. {
    563.     switch (tgtCPU) {
    564.         case GLB_CORE_ID_LP:
    565.             IPC_M0_Trigger_LP(src);
    566.             break;
    567.         case GLB_CORE_ID_D0:
    568.             IPC_M0_Trigger_D0(src);
    569.             break;
    570.         default:
    571.             break;
    572.     }
    573. }
    574.  
    575. /****************************************************************************/ /**
    576.  * @brief  LP trigger IPC interrupt to CPUx
    577.  *
    578.  * @param  tgtCPU: Target CPU
    579.  *
    580.  * @param  src: IPC interrupt source
    581.  *
    582.  * @return None
    583.  *
    584. *******************************************************************************/
    585. void IPC_LP_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
    586. {
    587.     switch (tgtCPU) {
    588.         case GLB_CORE_ID_M0:
    589.             IPC_LP_Trigger_M0(src);
    590.             break;
    591.         case GLB_CORE_ID_D0:
    592.             IPC_LP_Trigger_D0(src);
    593.             break;
    594.         default:
    595.             break;
    596.     }
    597. }
    598.  
    599. /****************************************************************************/ /**
    600.  * @brief  D0 trigger IPC interrupt to CPUx
    601.  *
    602.  * @param  tgtCPU: Target CPU
    603.  *
    604.  * @param  src: IPC interrupt source
    605.  *
    606.  * @return None
    607.  *
    608. *******************************************************************************/
    609. void IPC_D0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
    610. {
    611.     switch (tgtCPU) {
    612.         case GLB_CORE_ID_M0:
    613.             IPC_D0_Trigger_M0(src);
    614.             break;
    615.         case GLB_CORE_ID_LP:
    616.             IPC_D0_Trigger_LP(src);
    617.             break;
    618.         default:
    619.             break;
    620.     }
    621. }
    622.  
    623. /****************************************************************************/ /**
    624.  * @brief  D0 trigger IPC interrupt to D1
    625.  *
    626.  * @param  src: D0 IPC interrupt source
    627.  *
    628.  * @return None
    629.  *
    630. *******************************************************************************/
    631. void IPC_Trigger_Target_CPU(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src)
    632. {
    633.     GLB_CORE_ID_Type localCPU = GLB_Get_Core_Type();
    634.  
    635.     switch (localCPU) {
    636.         case GLB_CORE_ID_M0:
    637.             IPC_M0_Trigger_CPUx(tgtCPU, src);
    638.             break;
    639.         case GLB_CORE_ID_LP:
    640.             IPC_LP_Trigger_CPUx(tgtCPU, src);
    641.             break;
    642.         case GLB_CORE_ID_D0:
    643.             IPC_D0_Trigger_CPUx(tgtCPU, src);
    644.             break;
    645.         default:
    646.             break;
    647.     }
    648. }
    649.  
    650. /****************************************************************************/ /**
    651.  * @brief  D0 trigger IPC interrupt to D1
    652.  *
    653.  * @param  src: D0 IPC interrupt source
    654.  *
    655.  * @return None
    656.  *
    657. *******************************************************************************/
    658. void IPC_Common_Interrupt_Handler(uint32_t irqStatus, ipcIntCallback *callBack[GLB_CORE_ID_MAX - 1])
    659. {
    660.     uint32_t tmp;
    661.     uint32_t grp = 0;
    662.  
    663.     for (grp = 0; grp < GLB_CORE_ID_MAX - 1; grp++) {
    664.         tmp = (irqStatus >> (16 * grp)) & 0xffff;
    665.         if (tmp != 0) {
    666.             if (callBack[grp] != NULL) {
    667.                 callBack[grp](tmp);
    668.             }
    669.         }
    670.     }
    671. }
    672.  
    673. /****************************************************************************/ /**
    674.  * @brief  M0 IPC IRQ handler
    675.  *
    676.  * @param  None
    677.  *
    678.  * @return None
    679.  *
    680. *******************************************************************************/
    681. #ifndef BFLB_USE_HAL_DRIVER
    682. void IPC_M0_IRQHandler(void)
    683. {
    684.     uint32_t irqStatus;
    685.     irqStatus = IPC_M0_Get_Int_Raw_Status();
    686.     IPC_Common_Interrupt_Handler(irqStatus, m0IpcIntCbfArra);
    687.     IPC_M0_Clear_Int_By_Word(irqStatus);
    688. }
    689. #endif
    690.  
    691. /****************************************************************************/ /**
    692.  * @brief  LP IPC IRQ handler
    693.  *
    694.  * @param  None
    695.  *
    696.  * @return None
    697.  *
    698. *******************************************************************************/
    699. #ifndef BFLB_USE_HAL_DRIVER
    700. void IPC_LP_IRQHandler(void)
    701. {
    702.     uint32_t irqStatus;
    703.     irqStatus = IPC_LP_Get_Int_Raw_Status();
    704.     IPC_Common_Interrupt_Handler(irqStatus, lpIpcIntCbfArra);
    705.     IPC_LP_Clear_Int_By_Word(irqStatus);
    706. }
    707. #endif
    708.  
    709. /****************************************************************************/ /**
    710.  * @brief  D0 IPC IRQ handler
    711.  *
    712.  * @param  None
    713.  *
    714.  * @return None
    715.  *
    716. *******************************************************************************/
    717. #ifndef BFLB_USE_HAL_DRIVER
    718. void IPC_D0_IRQHandler(void)
    719. {
    720.     uint32_t irqStatus;
    721.     irqStatus = IPC_D0_Get_Int_Raw_Status();
    722.     IPC_Common_Interrupt_Handler(irqStatus, d0IpcIntCbfArra);
    723.     IPC_D0_Clear_Int_By_Word(irqStatus);
    724. }
    725. #endif
    726.  
    727. /*@} end of group IPC_Public_Functions */
    728.  
    729. /*@} end of group IPC */
    730.  
    731. /*@} end of group BL606P_Peripheral_Driver */

    三、总结 

    基本试验了IPC通讯，寄存器和触发动作应该是没问题的；看来后续要使用M1S_BL808_SDK作为开发主力的SDK了，好多函数封装了，功能实现的也比较好；只是目前只能在Linux下的开发环境使用，对于笔记本性能有限，懒得开虚拟机的我，还是eciplse的Windows客户端使用起来更方便一点。

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  • 原文地址：https://blog.csdn.net/DINGDING_GO/article/details/133466986