16、XDC引脚约束

（1）普通IO约束

set_property PACKAGE_PIN AG11 [get_ports CLK_100M]
set_property IOSTANDARD LVCMOS33 [get_ports CLK_100M]

（2）差分时钟约束

set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS} [get_ports sys_clk_i_clk_p]
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVDS} [get_ports sys_clk_i_clk_n]

（3）GT收发器专用参考时钟约束

set_property LOC “管脚编号” [get_ports “端口名称”]

## XDC generated for xc7z100-ffg900-2 device
# 125.0MHz GT Reference clock constraint
create_clock -name GT_REFCLK1 -period 8.0	 [get_ports GTXQ1_P]
####################### GT reference clock LOC #######################
set_property LOC AC7 [get_ports GTXQ1_N]
set_property LOC AC8 [get_ports GTXQ1_P]

（4）收发器MGT通道约束

set_property LOC “ GTXE2_CHANNEL_X* Y * ” [get_cells “gtxe_2例化路径”]

set_property LOC GTXE2_CHANNEL_X0Y6 [get_cells aurora_module_i/inst/aurora_8b10b_0_core_i/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt0_aurora_8b10b_0_i/gtxe2_i]
set_property LOC GTXE2_CHANNEL_X0Y7 [get_cells aurora_module_i/inst/aurora_8b10b_0_core_i/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt1_aurora_8b10b_0_i/gtxe2_i]

（5）差分信号约束

set_property PACKAGE_PIN N18 [get_ports TMDS_clk_p]
set_property IOSTANDARD LVDS [get_ports TMDS_clk_p]