FPGA project ： volt

module top(
    input   wire            sys_clk     ,
    input   wire            sys_rst_n   ,
    input   wire    [7:0]   ad_data     ,
 
    output  wire            ds          ,
    output  wire            oe          ,
    output  wire            shcp        ,
    output  wire            stcp        ,
    output  wire            ad_clk
);
 
 
    // 例化间连线
    wire    [15:0]          volt_w      ;
    wire    [19:00]         data_w      ;
    assign                  data_w = {4'b0000,volt_w} ;
    wire    [05:00]         point_w     ;
    assign                  point_w = 6'b001_000 ;
    wire                    sign_w      ;
    wire                    seg_en_w    ;
    assign                  seg_en_w = 1'b1 ;
dig_volt dig_volt_insert(
    .sys_clk                ( sys_clk    ) ,
    .sys_rst_n              ( sys_rst_n  ) ,
    .ad_data                ( ad_data    ) ,
    .volt                   ( volt_w     ) ,
    .sign                   ( sign_w     ) ,
    .ad_clk                 ( ad_clk     )
);
seg_595_dynamic seg_595_dynamic_insert(
    .sys_clk                ( sys_clk    ) ,
    .sys_rst_n              ( sys_rst_n  ) ,
    .data                   ( data_w     ) ,
    .point                  ( point_w    ) ,
    .sign                   ( sign_w     ) ,
    .seg_en                 ( seg_en_w   ) ,
    .ds                     ( ds         ) ,
    .oe                     ( oe         ) ,
    .shcp                   ( shcp       ) ,
    .stcp                   ( stcp       )    
);
endmodule

module dig_volt(
    input   wire            sys_clk     ,
    input   wire            sys_rst_n   ,
    input   wire    [7:0]   ad_data     ,
 
    output  reg     [15:0]  volt        ,
    output  reg             sign        ,
    output  wire            ad_clk
);
    // reg signal define
    reg                 cnt_ad_clk  ;
    reg                 ad_clk_reg  ; // 四分频。
    reg     [19:0]      cnt_1024    ;
    reg                 sum_en      ;
    reg                 sum_en_reg1 ;
    reg                 sum_en_reg2 ;
    reg     [19:0]      sum_1024    ;
    reg     [19:0]      data_medium ;
    reg     [19:0]      data_n_fenmm;
    reg     [19:0]      data_p_fenmm;
    reg     [28:0]      data_n      ;
    reg     [28:0]      data_p      ;
    reg     [15:0]      volt_reg    ;
 
    // reg                 cnt_ad_clk  ;
    always @(posedge sys_clk or negedge sys_rst_n) 
        if(~sys_rst_n) 
            cnt_ad_clk <= 1'b0 ;
        else 
            cnt_ad_clk <= cnt_ad_clk + 1'b1 ; // 溢出自动归零
 
    // reg                 ad_clk_reg  ;
    always @(posedge sys_clk or negedge sys_rst_n) 
        if(~sys_rst_n)
            ad_clk_reg <= 1'b0 ;
        else if(cnt_ad_clk == 1'b1)
            ad_clk_reg <= ~ad_clk_reg ;
 
    // reg     [19:0]      cnt_1024    ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n)
            cnt_1024 <= 20'd0 ;
        else if(cnt_1024 == 20'd1025)
            cnt_1024 <= cnt_1024 ;
        else 
            cnt_1024 <= cnt_1024 + 1'b1 ;
    // reg                 sum_en      ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n)
            sum_en <= 1'b0 ;
        else if(cnt_1024 == 20'd1025)
            sum_en <= 1'b1 ;
        else 
            sum_en <= 1'b0 ;
    // reg                 sum_en_reg1  ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n)
            sum_en_reg1 <= 1'b0 ;
        else 
            sum_en_reg1 <= sum_en ;    
    // reg                 sum_en_reg2  ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n)
            sum_en_reg2 <= 1'b0 ;
        else 
            sum_en_reg2 <= sum_en_reg1 ;
    // reg     [19:0]      sum_1024    ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n)
            sum_1024 <= 20'd0 ;
        else if(cnt_1024 >= 20'd1 && cnt_1024 <= 20'd1024)
            sum_1024 <= sum_1024 + ad_data ;
        else
            sum_1024 <= sum_1024 ;
 
    // reg     [19:0]      data_medium ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n)
            data_medium <= 20'd0 ;
        else if(cnt_1024 == 20'd1025)
            data_medium <= sum_1024 / 20'd1024 ;
        else 
            data_medium <= data_medium ;
    // reg     [19:0]      data_n_fenmm;
    // reg     [19:0]      data_p_fenmm;
    always @(posedge ad_clk_reg or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            data_n_fenmm <= 20'd0 ;
            data_p_fenmm <= 20'd0 ;
        end else begin
            if(sum_en == 1'b1) begin
                data_n_fenmm <= data_medium  + 1'd1 ;
                data_p_fenmm <= 20'd256 - data_medium;
            end
        end
    end
    // reg     [28:0]      data_n      ;
    // reg     [28:0]      data_p      ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            data_n <= 26'd0 ;
            data_p <= 26'd0 ;
        end else begin
            if(sum_en_reg1 == 1'b1) begin
                data_n <= 26'd40960000 / data_n_fenmm ;
                data_p <= 26'd40960000 / data_p_fenmm  ;
            end else begin
                data_n <= 26'd0 ;
                data_p <= 26'd0 ;
            end
        end
    end
    // reg     [15:0]      volt_reg    ;
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n) 
            volt_reg <= 16'd0 ;
        else if(sum_en_reg2 == 1'b1 && ad_data >= data_medium)
            volt_reg <= ((data_p * (ad_data - data_medium)) >> 4'd13) ;
        else if(sum_en_reg2 == 1'b1 && ad_data < data_medium)
            volt_reg <= ((data_n * (data_medium - ad_data)) >> 4'd13) ;
        else 
            volt_reg <= 16'd0 ;
    // reg     [15:0]  volt        ,
    always @(posedge ad_clk_reg or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            volt <= 16'd0 ;
        end else begin
            volt <= volt_reg ;
        end
    end
    // sign
    always @(posedge ad_clk_reg or negedge sys_rst_n) 
        if(~sys_rst_n) 
            sign <= 1'b0 ;
        else if(sum_en_reg2 == 1'b1 && ad_data < data_medium) // 小于中值有符号位.
            sign <= 1'b1 ;
        else 
            sign <= 1'b0 ;
    // wire             ad_clk
    assign ad_clk = ~ad_clk_reg ;
endmodule

`timescale 1ns/1ns
module test_top();
    reg             sys_clk     ;
    reg             sys_rst_n   ;
    reg     [7:0]   ad_data     ;
 
    reg             data_en     ; // 当数据使能信号为低电平，ad_data == 125 ;高，把ad_data_reg 赋值给ad_data.
    reg     [7:0]   ad_data_reg ; // 数据寄存。
 
    wire            ds          ;
    wire            oe          ;
    wire            shcp        ;
    wire            stcp        ;
    wire            ad_clk      ;
 
top top_insert(
    .sys_clk                ( sys_clk    ) ,
    .sys_rst_n              ( sys_rst_n  ) ,
    .ad_data                ( ad_data    ) ,
 
    .ds                     ( ds         ) ,
    .oe                     ( oe         ) ,
    .shcp                   ( shcp       ) ,
    .stcp                   ( stcp       ) ,
    .ad_clk                 ( ad_clk     )
);
 
    parameter CYCLE = 20 ;
    initial begin
        sys_clk = 1'b1      ;
        sys_rst_n <= 1'b0   ;
        data_en   <= 1'b0 ;
        #(CYCLE * 10)       ;
        sys_rst_n <= 1'b1   ;
        #(CYCLE * 4 * 5000) ;
        data_en <= 1'b1 ;
    end
    always #(CYCLE / 2) sys_clk = ~sys_clk ;
    // reg             data_en     ; // 当数据使能信号为低电平，ad_data == 125 ;高，把ad_data_reg 赋值给ad_data.
    // reg     [7:0]   ad_data_reg ; // 数据寄存。
    always @(posedge sys_clk or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            ad_data_reg <= 1'b0 ;
        end else begin
            ad_data_reg <= ad_data_reg + 1'b1 ;
        end
    end
    // reg     [7:0]   ad_data     ;
    always @(posedge ad_clk or negedge sys_rst_n) begin
        if(~sys_rst_n) begin
            ad_data <= 1'b0 ;
        end else begin
            if(data_en == 1'b0) begin
                ad_data <= 8'd125 ;
            end else begin
                ad_data <= ad_data_reg ;
            end
        end
    end
 
 
endmodule