verilog学习笔记（1）module实例化2

移位寄存器+多路选择器

我的代码：

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] w1;
    wire [7:0] w2;
    wire [7:0] w3;
    
    my_dff8 my_dff8_1(
        .clk(clk),
        .d(d),
        .q(w1)
    );
    
    my_dff8 my_dff8_2(
        .clk(clk),
        .d(w1),
        .q(w2)
    );
    
    my_dff8 my_dff8_3(
        .clk(clk),
        .d(w2),
        .q(w3)
    );
    
    always@(d or w1 or w2 or w3 or sel)
        begin
            if(sel == 2'b00 )
                q <= d;
            else if(sel == 2'b01 )
               q <= w1;
            else if(sel == 2'b10 )
               q <= w2;
            else
               q <= w3;
        end
 
endmodule

 答案：

module top_module (
	input clk,
	input [7:0] d,
	input [1:0] sel,
	output reg [7:0] q
);
 
	wire [7:0] o1, o2, o3;		// output of each my_dff8
	
	// Instantiate three my_dff8s
	my_dff8 d1 ( clk, d, o1 );
	my_dff8 d2 ( clk, o1, o2 );
	my_dff8 d3 ( clk, o2, o3 );
 
	// This is one way to make a 4-to-1 multiplexer
	always @(*)		// Combinational always block
		case(sel)
			2'h0: q = d;
			2'h1: q = o1;
			2'h2: q = o2;
			2'h3: q = o3;
		endcase
 
endmodule