• RK3568 CAN驱动更新说明

    RK3568 CAN问题：同时收发数据一段时间（几秒钟）can出现错误收发功能异常，必须重新down、up恢复正常
    内核更新rockchip_canfd.c、iopoll.h，配置Networking support  --->CAN bus subsystem support  --->CAN Device Drivers  --->Rockchip CANFD controller, make ARCH=arm64 menuconfig;内核配置后将.config覆盖到arch/arm64/configs/rockchip_linux_defconfig
    修改设备树can节点.arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-linux.dts
    compatible = "rockchip,rk3568-can-2.0",assigned-clock-rates = <300000000>;//如果CAN的比特率1M建议修改CAN时钟到300M，信号更稳定
    ./build.sh kernerl
    注意：测试时两个节点帧ID不能相同，否则会发生数据错误，且负载率宜控制在30%以内
    【负载率计算】
    假设报文以定周期发送，总线上的报文只有数据帧一种类型，不存在远程帧、错误帧和过载帧这三种类型。因此每帧报文包括：帧起始（1bit）、仲裁域（29bit）、控制域（6bit）、数据域（8×8bit）、循环冗余码域（15bit）、应答域（2bit）和帧结尾（7bit），共124位。
    假设每秒发送的数据帧数为185帧
    对于高速CAN总线（500kbps）的负载率 = frac{185*124}\{500*1000}*100\% = 4.58\%
    对于低速CAN总线（250kbps）的负载率 = frac{185*124}\{250*1000}*100\% = 9.16\%
    【rockchip_canfd.c】 
    1. // SPDX-License-Identifier: GPL-2.0
    2. /*
    3.  * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
    4.  * Rockchip CANFD driver
    5.  */
    6.  
    7. #include <linux/delay.h>
    8. #include <linux/iopoll.h>
    9. #include <linux/pinctrl/consumer.h>
    10. #include <linux/clk.h>
    11. #include <linux/errno.h>
    12. #include <linux/init.h>
    13. #include <linux/interrupt.h>
    14. #include <linux/io.h>
    15. #include <linux/kernel.h>
    16. #include <linux/module.h>
    17. #include <linux/netdevice.h>
    18. #include <linux/of.h>
    19. #include <linux/of_device.h>
    20. #include <linux/platform_device.h>
    21. #include <linux/skbuff.h>
    22. #include <linux/spinlock.h>
    23. #include <linux/string.h>
    24. #include <linux/types.h>
    25. #include <linux/can/dev.h>
    26. #include <linux/can/error.h>
    27. #include <linux/can/led.h>
    28. #include <linux/reset.h>
    29. #include <linux/pm_runtime.h>
    30.  
    31. /* registers definition */
    32. enum rockchip_canfd_reg {
    33.         CAN_MODE = 0x00,
    34.         CAN_CMD = 0x04,
    35.         CAN_STATE = 0x08,
    36.         CAN_INT = 0x0c,
    37.         CAN_INT_MASK = 0x10,
    38.         CAN_LOSTARB_CODE = 0x28,
    39.         CAN_ERR_CODE = 0x2c,
    40.         CAN_RX_ERR_CNT = 0x34,
    41.         CAN_TX_ERR_CNT = 0x38,
    42.         CAN_IDCODE = 0x3c,
    43.         CAN_IDMASK = 0x40,
    44.         CAN_TX_CHECK_FIC = 0x50,
    45.         CAN_NBTP = 0x100,
    46.         CAN_DBTP = 0x104,
    47.         CAN_TDCR = 0x108,
    48.         CAN_TSCC = 0x10c,
    49.         CAN_TSCV = 0x110,
    50.         CAN_TXEFC = 0x114,
    51.         CAN_RXFC = 0x118,
    52.         CAN_AFC = 0x11c,
    53.         CAN_IDCODE0 = 0x120,
    54.         CAN_IDMASK0 = 0x124,
    55.         CAN_IDCODE1 = 0x128,
    56.         CAN_IDMASK1 = 0x12c,
    57.         CAN_IDCODE2 = 0x130,
    58.         CAN_IDMASK2 = 0x134,
    59.         CAN_IDCODE3 = 0x138,
    60.         CAN_IDMASK3 = 0x13c,
    61.         CAN_IDCODE4 = 0x140,
    62.         CAN_IDMASK4 = 0x144,
    63.         CAN_TXFIC = 0x200,
    64.         CAN_TXID = 0x204,
    65.         CAN_TXDAT0 = 0x208,
    66.         CAN_TXDAT1 = 0x20c,
    67.         CAN_TXDAT2 = 0x210,
    68.         CAN_TXDAT3 = 0x214,
    69.         CAN_TXDAT4 = 0x218,
    70.         CAN_TXDAT5 = 0x21c,
    71.         CAN_TXDAT6 = 0x220,
    72.         CAN_TXDAT7 = 0x224,
    73.         CAN_TXDAT8 = 0x228,
    74.         CAN_TXDAT9 = 0x22c,
    75.         CAN_TXDAT10 = 0x230,
    76.         CAN_TXDAT11 = 0x234,
    77.         CAN_TXDAT12 = 0x238,
    78.         CAN_TXDAT13 = 0x23c,
    79.         CAN_TXDAT14 = 0x240,
    80.         CAN_TXDAT15 = 0x244,
    81.         CAN_RXFIC = 0x300,
    82.         CAN_RXID = 0x304,
    83.         CAN_RXTS = 0x308,
    84.         CAN_RXDAT0 = 0x30c,
    85.         CAN_RXDAT1 = 0x310,
    86.         CAN_RXDAT2 = 0x314,
    87.         CAN_RXDAT3 = 0x318,
    88.         CAN_RXDAT4 = 0x31c,
    89.         CAN_RXDAT5 = 0x320,
    90.         CAN_RXDAT6 = 0x324,
    91.         CAN_RXDAT7 = 0x328,
    92.         CAN_RXDAT8 = 0x32c,
    93.         CAN_RXDAT9 = 0x330,
    94.         CAN_RXDAT10 = 0x334,
    95.         CAN_RXDAT11 = 0x338,
    96.         CAN_RXDAT12 = 0x33c,
    97.         CAN_RXDAT13 = 0x340,
    98.         CAN_RXDAT14 = 0x344,
    99.         CAN_RXDAT15 = 0x348,
    100.         CAN_RXFRD = 0x400,
    101.         CAN_TXEFRD = 0x500,
    102. };
    103.  
    104. enum {
    105.         ROCKCHIP_CANFD_MODE = 0,
    106.         ROCKCHIP_CAN_MODE,
    107.         ROCKCHIP_RK3568_CAN_MODE,
    108. };
    109.  
    110. #define DATE_LENGTH_12_BYTE     (0x9)
    111. #define DATE_LENGTH_16_BYTE     (0xa)
    112. #define DATE_LENGTH_20_BYTE     (0xb)
    113. #define DATE_LENGTH_24_BYTE     (0xc)
    114. #define DATE_LENGTH_32_BYTE     (0xd)
    115. #define DATE_LENGTH_48_BYTE     (0xe)
    116. #define DATE_LENGTH_64_BYTE     (0xf)
    117.  
    118. #define CAN_TX0_REQ             BIT(0)
    119. #define CAN_TX1_REQ             BIT(1)
    120. #define CAN_TX_REQ_FULL         ((CAN_TX0_REQ) | (CAN_TX1_REQ))
    121.  
    122. #define MODE_FDOE               BIT(15)
    123. #define MODE_BRSD               BIT(13)
    124. #define MODE_SPACE_RX           BIT(12)
    125. #define MODE_AUTO_RETX          BIT(10)
    126. #define MODE_RXSORT             BIT(7)
    127. #define MODE_TXORDER            BIT(6)
    128. #define MODE_RXSTX              BIT(5)
    129. #define MODE_LBACK              BIT(4)
    130. #define MODE_SILENT             BIT(3)
    131. #define MODE_SELF_TEST          BIT(2)
    132. #define MODE_SLEEP              BIT(1)
    133. #define RESET_MODE              0
    134. #define WORK_MODE               BIT(0)
    135.  
    136. #define RX_FINISH_INT           BIT(0)
    137. #define TX_FINISH_INT           BIT(1)
    138. #define ERR_WARN_INT            BIT(2)
    139. #define RX_BUF_OV_INT           BIT(3)
    140. #define PASSIVE_ERR_INT         BIT(4)
    141. #define TX_LOSTARB_INT          BIT(5)
    142. #define BUS_ERR_INT             BIT(6)
    143. #define RX_FIFO_FULL_INT        BIT(7)
    144. #define RX_FIFO_OV_INT          BIT(8)
    145. #define BUS_OFF_INT             BIT(9)
    146. #define BUS_OFF_RECOVERY_INT    BIT(10)
    147. #define TSC_OV_INT              BIT(11)
    148. #define TXE_FIFO_OV_INT         BIT(12)
    149. #define TXE_FIFO_FULL_INT       BIT(13)
    150. #define WAKEUP_INT              BIT(14)
    151.  
    152. #define ERR_TYPE_MASK           GENMASK(28, 26)
    153. #define ERR_TYPE_SHIFT          26
    154. #define BIT_ERR                 0
    155. #define STUFF_ERR               1
    156. #define FORM_ERR                2
    157. #define ACK_ERR                 3
    158. #define CRC_ERR                 4
    159. #define ERR_DIR_RX              BIT(25)
    160. #define ERR_LOC_MASK            GENMASK(15, 0)
    161.  
    162. /* Nominal Bit Timing & Prescaler Register (NBTP) */
    163. #define NBTP_MODE_3_SAMPLES     BIT(31)
    164. #define NBTP_NSJW_SHIFT         24
    165. #define NBTP_NSJW_MASK          (0x7f << NBTP_NSJW_SHIFT)
    166. #define NBTP_NBRP_SHIFT         16
    167. #define NBTP_NBRP_MASK          (0xff << NBTP_NBRP_SHIFT)
    168. #define NBTP_NTSEG2_SHIFT       8
    169. #define NBTP_NTSEG2_MASK        (0x7f << NBTP_NTSEG2_SHIFT)
    170. #define NBTP_NTSEG1_SHIFT       0
    171. #define NBTP_NTSEG1_MASK        (0x7f << NBTP_NTSEG1_SHIFT)
    172.  
    173. /* Data Bit Timing & Prescaler Register (DBTP) */
    174. #define DBTP_MODE_3_SAMPLES     BIT(21)
    175. #define DBTP_DSJW_SHIFT         17
    176. #define DBTP_DSJW_MASK          (0xf << DBTP_DSJW_SHIFT)
    177. #define DBTP_DBRP_SHIFT         9
    178. #define DBTP_DBRP_MASK          (0xff << DBTP_DBRP_SHIFT)
    179. #define DBTP_DTSEG2_SHIFT       5
    180. #define DBTP_DTSEG2_MASK        (0xf << DBTP_DTSEG2_SHIFT)
    181. #define DBTP_DTSEG1_SHIFT       0
    182. #define DBTP_DTSEG1_MASK        (0x1f << DBTP_DTSEG1_SHIFT)
    183.  
    184. /* Transmitter Delay Compensation Register (TDCR) */
    185. #define TDCR_TDCO_SHIFT         1
    186. #define TDCR_TDCO_MASK          (0x3f << TDCR_TDCO_SHIFT)
    187. #define TDCR_TDC_ENABLE         BIT(0)
    188.  
    189. #define TX_FD_ENABLE            BIT(5)
    190. #define TX_FD_BRS_ENABLE        BIT(4)
    191.  
    192. #define FIFO_ENABLE             BIT(0)
    193. #define RX_FIFO_CNT0_SHIFT      4
    194. #define RX_FIFO_CNT0_MASK       (0x7 << RX_FIFO_CNT0_SHIFT)
    195. #define RX_FIFO_CNT1_SHIFT      5
    196. #define RX_FIFO_CNT1_MASK       (0x7 << RX_FIFO_CNT1_SHIFT)
    197.  
    198. #define FORMAT_SHIFT            7
    199. #define FORMAT_MASK             (0x1 << FORMAT_SHIFT)
    200. #define RTR_SHIFT               6
    201. #define RTR_MASK                (0x1 << RTR_SHIFT)
    202. #define FDF_SHIFT               5
    203. #define FDF_MASK                (0x1 << FDF_SHIFT)
    204. #define BRS_SHIFT               4
    205. #define BRS_MASK                (0x1 << BRS_SHIFT)
    206. #define DLC_SHIFT               0
    207. #define DLC_MASK                (0xF << DLC_SHIFT)
    208.  
    209. #define CAN_RF_SIZE             0x48
    210. #define CAN_TEF_SIZE            0x8
    211. #define CAN_TXEFRD_OFFSET(n)    (CAN_TXEFRD + CAN_TEF_SIZE * (n))
    212. #define CAN_RXFRD_OFFSET(n)     (CAN_RXFRD + CAN_RF_SIZE * (n))
    213.  
    214. #define CAN_RX_FILTER_MASK      0x1fffffff
    215.  
    216. #define DRV_NAME        "rockchip_canfd"
    217.  
    218. /* rockchip_canfd private data structure */
    219.  
    220. struct rockchip_canfd {
    221.         struct can_priv can;
    222.         struct device *dev;
    223.         struct clk_bulk_data *clks;
    224.         int num_clks;
    225.         struct reset_control *reset;
    226.         void __iomem *base;
    227.         u32 irqstatus;
    228.         unsigned long mode;
    229.         int rx_fifo_shift;
    230.         u32 rx_fifo_mask;
    231.         bool txtorx;
    232.         u32 tx_invalid[4];
    233.         struct delayed_work tx_err_work;
    234. };
    235.  
    236. static inline u32 rockchip_canfd_read(const struct rockchip_canfd *priv,
    237.                                       enum rockchip_canfd_reg reg)
    238. {
    239.         return readl(priv->base + reg);
    240. }
    241.  
    242. static inline void rockchip_canfd_write(const struct rockchip_canfd *priv,
    243.                                         enum rockchip_canfd_reg reg, u32 val)
    244. {
    245.         writel(val, priv->base + reg);
    246. }
    247.  
    248. static const struct can_bittiming_const rockchip_canfd_bittiming_const = {
    249.         .name = DRV_NAME,
    250.         .tseg1_min = 1,
    251.         .tseg1_max = 128,
    252.         .tseg2_min = 1,
    253.         .tseg2_max = 128,
    254.         .sjw_max = 128,
    255.         .brp_min = 1,
    256.         .brp_max = 256,
    257.         .brp_inc = 2,
    258. };
    259.  
    260. static const struct can_bittiming_const rockchip_canfd_data_bittiming_const = {
    261.         .name = DRV_NAME,
    262.         .tseg1_min = 1,
    263.         .tseg1_max = 32,
    264.         .tseg2_min = 1,
    265.         .tseg2_max = 16,
    266.         .sjw_max = 16,
    267.         .brp_min = 1,
    268.         .brp_max = 256,
    269.         .brp_inc = 2,
    270. };
    271.  
    272. static int set_reset_mode(struct net_device *ndev)
    273. {
    274.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    275.  
    276.         reset_control_assert(rcan->reset);
    277.         udelay(2);
    278.         reset_control_deassert(rcan->reset);
    279.  
    280.         rockchip_canfd_write(rcan, CAN_MODE, 0);
    281.  
    282.         netdev_dbg(ndev, "%s MODE=0x%08x\n", __func__,
    283.                    rockchip_canfd_read(rcan, CAN_MODE));
    284.  
    285.         return 0;
    286. }
    287.  
    288. static int set_normal_mode(struct net_device *ndev)
    289. {
    290.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    291.         u32 val;
    292.  
    293.         val = rockchip_canfd_read(rcan, CAN_MODE);
    294.         val |= WORK_MODE;
    295.         rockchip_canfd_write(rcan, CAN_MODE, val);
    296.  
    297.         netdev_dbg(ndev, "%s MODE=0x%08x\n", __func__,
    298.                    rockchip_canfd_read(rcan, CAN_MODE));
    299.         return 0;
    300. }
    301.  
    302. /* bittiming is called in reset_mode only */
    303. static int rockchip_canfd_set_bittiming(struct net_device *ndev)
    304. {
    305.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    306.         const struct can_bittiming *bt = &rcan->can.bittiming;
    307.         const struct can_bittiming *dbt = &rcan->can.data_bittiming;
    308.         u16 brp, sjw, tseg1, tseg2;
    309.         u32 reg_btp;
    310.  
    311.         brp = (bt->brp >> 1) - 1;
    312.         sjw = bt->sjw - 1;
    313.         tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
    314.         tseg2 = bt->phase_seg2 - 1;
    315.         reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
    316.                   (tseg1 << NBTP_NTSEG1_SHIFT) |
    317.                   (tseg2 << NBTP_NTSEG2_SHIFT);
    318.  
    319.         if (rcan->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
    320.                 reg_btp |= NBTP_MODE_3_SAMPLES;
    321.  
    322.         rockchip_canfd_write(rcan, CAN_NBTP, reg_btp);
    323.  
    324.         if (rcan->can.ctrlmode & CAN_CTRLMODE_FD) {
    325.                 reg_btp = 0;
    326.                 brp = (dbt->brp >> 1) - 1;
    327.                 sjw = dbt->sjw - 1;
    328.                 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
    329.                 tseg2 = dbt->phase_seg2 - 1;
    330.  
    331.                 if (dbt->bitrate > 2200000) {
    332.                         u32 tdco;
    333.  
    334.                         /* Equation based on Bosch's ROCKCHIP_CAN User Manual's
    335.                          * Transmitter Delay Compensation Section
    336.                          */
    337.                         tdco = (rcan->can.clock.freq / dbt->bitrate) * 2 / 3;
    338.                         /* Max valid TDCO value is 63 */
    339.                         if (tdco > 63)
    340.                                 tdco = 63;
    341.  
    342.                         rockchip_canfd_write(rcan, CAN_TDCR,
    343.                                              (tdco << TDCR_TDCO_SHIFT) |
    344.                                              TDCR_TDC_ENABLE);
    345.                 }
    346.  
    347.                 reg_btp |= (brp << DBTP_DBRP_SHIFT) |
    348.                            (sjw << DBTP_DSJW_SHIFT) |
    349.                            (tseg1 << DBTP_DTSEG1_SHIFT) |
    350.                            (tseg2 << DBTP_DTSEG2_SHIFT);
    351.  
    352.                 if (rcan->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
    353.                         reg_btp |= DBTP_MODE_3_SAMPLES;
    354.  
    355.                 rockchip_canfd_write(rcan, CAN_DBTP, reg_btp);
    356.         }
    357.  
    358.         netdev_dbg(ndev, "%s NBTP=0x%08x, DBTP=0x%08x, TDCR=0x%08x\n", __func__,
    359.                    rockchip_canfd_read(rcan, CAN_NBTP),
    360.                    rockchip_canfd_read(rcan, CAN_DBTP),
    361.                    rockchip_canfd_read(rcan, CAN_TDCR));
    362.         return 0;
    363. }
    364.  
    365. static int rockchip_canfd_get_berr_counter(const struct net_device *ndev,
    366.                                            struct can_berr_counter *bec)
    367. {
    368.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    369.         int err;
    370.  
    371.         err = pm_runtime_get_sync(rcan->dev);
    372.         if (err < 0) {
    373.                 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
    374.                            __func__, err);
    375.                 return err;
    376.         }
    377.  
    378.         bec->rxerr = rockchip_canfd_read(rcan, CAN_RX_ERR_CNT);
    379.         bec->txerr = rockchip_canfd_read(rcan, CAN_TX_ERR_CNT);
    380.  
    381.         pm_runtime_put(rcan->dev);
    382.  
    383.         netdev_dbg(ndev, "%s RX_ERR_CNT=0x%08x, TX_ERR_CNT=0x%08x\n", __func__,
    384.                    rockchip_canfd_read(rcan, CAN_RX_ERR_CNT),
    385.                    rockchip_canfd_read(rcan, CAN_TX_ERR_CNT));
    386.  
    387.         return 0;
    388. }
    389.  
    390. static int rockchip_canfd_start(struct net_device *ndev)
    391. {
    392.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    393.         u32 val;
    394.  
    395.         /* we need to enter the reset mode */
    396.         set_reset_mode(ndev);
    397.  
    398.         rockchip_canfd_write(rcan, CAN_INT_MASK, 0);
    399.  
    400.         /* RECEIVING FILTER, accept all */
    401.         rockchip_canfd_write(rcan, CAN_IDCODE, 0);
    402.         rockchip_canfd_write(rcan, CAN_IDMASK, CAN_RX_FILTER_MASK);
    403.         rockchip_canfd_write(rcan, CAN_IDCODE0, 0);
    404.         rockchip_canfd_write(rcan, CAN_IDMASK0, CAN_RX_FILTER_MASK);
    405.         rockchip_canfd_write(rcan, CAN_IDCODE1, 0);
    406.         rockchip_canfd_write(rcan, CAN_IDMASK1, CAN_RX_FILTER_MASK);
    407.         rockchip_canfd_write(rcan, CAN_IDCODE2, 0);
    408.         rockchip_canfd_write(rcan, CAN_IDMASK2, CAN_RX_FILTER_MASK);
    409.         rockchip_canfd_write(rcan, CAN_IDCODE3, 0);
    410.         rockchip_canfd_write(rcan, CAN_IDMASK3, CAN_RX_FILTER_MASK);
    411.         rockchip_canfd_write(rcan, CAN_IDCODE4, 0);
    412.         rockchip_canfd_write(rcan, CAN_IDMASK4, CAN_RX_FILTER_MASK);
    413.  
    414.         /* set mode */
    415.         val = rockchip_canfd_read(rcan, CAN_MODE);
    416.  
    417.         /* rx fifo enable */
    418.         rockchip_canfd_write(rcan, CAN_RXFC,
    419.                              rockchip_canfd_read(rcan, CAN_RXFC) | FIFO_ENABLE);
    420.  
    421.         /* Mode */
    422.         val |= MODE_FDOE;
    423.  
    424.         /* Loopback Mode */
    425.         if (rcan->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
    426.                 val |= MODE_SELF_TEST | MODE_LBACK;
    427.  
    428.         val |= MODE_AUTO_RETX;
    429.  
    430.         rockchip_canfd_write(rcan, CAN_MODE, val);
    431.  
    432.         rockchip_canfd_set_bittiming(ndev);
    433.  
    434.         set_normal_mode(ndev);
    435.  
    436.         rcan->can.state = CAN_STATE_ERROR_ACTIVE;
    437.  
    438.         netdev_dbg(ndev, "%s MODE=0x%08x, INT_MASK=0x%08x\n", __func__,
    439.                    rockchip_canfd_read(rcan, CAN_MODE),
    440.                    rockchip_canfd_read(rcan, CAN_INT_MASK));
    441.  
    442.         return 0;
    443. }
    444.  
    445. static int rockchip_canfd_stop(struct net_device *ndev)
    446. {
    447.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    448.  
    449.         rcan->can.state = CAN_STATE_STOPPED;
    450.         /* we need to enter reset mode */
    451.         set_reset_mode(ndev);
    452.  
    453.         /* disable all interrupts */
    454.         rockchip_canfd_write(rcan, CAN_INT_MASK, 0xffff);
    455.  
    456.         netdev_dbg(ndev, "%s MODE=0x%08x, INT_MASK=0x%08x\n", __func__,
    457.                    rockchip_canfd_read(rcan, CAN_MODE),
    458.                    rockchip_canfd_read(rcan, CAN_INT_MASK));
    459.         return 0;
    460. }
    461.  
    462. static int rockchip_canfd_set_mode(struct net_device *ndev,
    463.                                    enum can_mode mode)
    464. {
    465.         int err;
    466.  
    467.         switch (mode) {
    468.         case CAN_MODE_START:
    469.                 err = rockchip_canfd_start(ndev);
    470.                 if (err) {
    471.                         netdev_err(ndev, "starting CAN controller failed!\n");
    472.                         return err;
    473.                 }
    474.                 if (netif_queue_stopped(ndev))
    475.                         netif_wake_queue(ndev);
    476.                 break;
    477.  
    478.         default:
    479.                 return -EOPNOTSUPP;
    480.         }
    481.  
    482.         return 0;
    483. }
    484.  
    485. static void rockchip_canfd_tx_err_delay_work(struct work_struct *work)
    486. {
    487.         struct rockchip_canfd *rcan =
    488.                 container_of(work, struct rockchip_canfd, tx_err_work.work);
    489.         u32 mode, err_code, id;
    490.  
    491.         id = rockchip_canfd_read(rcan, CAN_TXID);
    492.         err_code = rockchip_canfd_read(rcan, CAN_ERR_CODE);
    493.         if (err_code & 0x1fe0000) {
    494.                 mode = rockchip_canfd_read(rcan, CAN_MODE);
    495.                 rockchip_canfd_write(rcan, CAN_MODE, 0);
    496.                 rockchip_canfd_write(rcan, CAN_MODE, mode);
    497.                 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
    498.                 schedule_delayed_work(&rcan->tx_err_work, 1);
    499.         } else if (rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && id & CAN_EFF_FLAG) {
    500.                 schedule_delayed_work(&rcan->tx_err_work, 1);
    501.         }
    502. }
    503.  
    504. /* transmit a CAN message
    505.  * message layout in the sk_buff should be like this:
    506.  * xx xx xx xx         ff         ll 00 11 22 33 44 55 66 77
    507.  * [ can_id ] [flags] [len] [can data (up to 8 bytes]
    508.  */
    509. static int rockchip_canfd_start_xmit(struct sk_buff *skb,
    510.                                      struct net_device *ndev)
    511. {
    512.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    513.         struct canfd_frame *cf = (struct canfd_frame *)skb->data;
    514.         u32 id, dlc;
    515.         u32 cmd = CAN_TX0_REQ;
    516.         int i;
    517.         unsigned long flags;
    518.  
    519.         if (can_dropped_invalid_skb(ndev, skb))
    520.                 return NETDEV_TX_OK;
    521.  
    522.         netif_stop_queue(ndev);
    523.  
    524.         if (rockchip_canfd_read(rcan, CAN_CMD) & CAN_TX0_REQ)
    525.                 cmd = CAN_TX1_REQ;
    526.  
    527.         /* Watch carefully on the bit sequence */
    528.         if (cf->can_id & CAN_EFF_FLAG) {
    529.                 /* Extended CAN ID format */
    530.                 id = cf->can_id & CAN_EFF_MASK;
    531.                 dlc = can_len2dlc(cf->len) & DLC_MASK;
    532.                 dlc |= FORMAT_MASK;
    533.  
    534.                 /* Extended frames remote TX request */
    535.                 if (cf->can_id & CAN_RTR_FLAG)
    536.                         dlc |= RTR_MASK;
    537.         } else {
    538.                 /* Standard CAN ID format */
    539.                 id = cf->can_id & CAN_SFF_MASK;
    540.                 dlc = can_len2dlc(cf->len) & DLC_MASK;
    541.  
    542.                 /* Standard frames remote TX request */
    543.                 if (cf->can_id & CAN_RTR_FLAG)
    544.                         dlc |= RTR_MASK;
    545.         }
    546.  
    547.         if ((rcan->can.ctrlmode & CAN_CTRLMODE_FD) && can_is_canfd_skb(skb)) {
    548.                 dlc |= TX_FD_ENABLE;
    549.                 if (cf->flags & CANFD_BRS)
    550.                         dlc |= TX_FD_BRS_ENABLE;
    551.         }
    552.  
    553.         if (rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && cf->can_id & CAN_EFF_FLAG)
    554.                 rockchip_canfd_write(rcan, CAN_MODE, rockchip_canfd_read(rcan, CAN_MODE) | MODE_RXSTX);
    555.         else
    556.                 rockchip_canfd_write(rcan, CAN_MODE, rockchip_canfd_read(rcan, CAN_MODE) & (~MODE_RXSTX));
    557.  
    558.         if (!rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && cf->can_id & CAN_EFF_FLAG) {
    559.                 /* Two frames are sent consecutively.
    560.                  * Before the first frame is tx finished,
    561.                  * the register of the second frame is configured.
    562.                  * Don't be interrupted in the middle.
    563.                  */
    564.                 local_irq_save(flags);
    565.                 rockchip_canfd_write(rcan, CAN_TXID, rcan->tx_invalid[1]);
    566.                 rockchip_canfd_write(rcan, CAN_TXFIC, rcan->tx_invalid[0]);
    567.                 rockchip_canfd_write(rcan, CAN_TXDAT0, rcan->tx_invalid[2]);
    568.                 rockchip_canfd_write(rcan, CAN_TXDAT1, rcan->tx_invalid[3]);
    569.                 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX0_REQ);
    570.                 rockchip_canfd_write(rcan, CAN_TXID, id);
    571.                 rockchip_canfd_write(rcan, CAN_TXFIC, dlc);
    572.                 for (i = 0; i < cf->len; i += 4)
    573.                         rockchip_canfd_write(rcan, CAN_TXDAT0 + i,
    574.                                              *(u32 *)(cf->data + i));
    575.                 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
    576.                 local_irq_restore(flags);
    577.                 can_put_echo_skb(skb, ndev, 0);
    579.                 return NETDEV_TX_OK;
    580.         }
    582.         rockchip_canfd_write(rcan, CAN_TXID, id);
    583.         rockchip_canfd_write(rcan, CAN_TXFIC, dlc);
    585.         for (i = 0; i < cf->len; i += 4)
    586.                 rockchip_canfd_write(rcan, CAN_TXDAT0 + i,
    587.                                      *(u32 *)(cf->data + i));
    589.         rockchip_canfd_write(rcan, CAN_CMD, CAN_TX0_REQ);
    591.         if (rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && cf->can_id & CAN_EFF_FLAG)
    592.                 schedule_delayed_work(&rcan->tx_err_work, 1);
    594.         can_put_echo_skb(skb, ndev, 0);
    596.         return NETDEV_TX_OK;
    597. }
    599. static int rockchip_canfd_rx(struct net_device *ndev)
    600. {
    601.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    602.         struct net_device_stats *stats = &ndev->stats;
    603.         struct canfd_frame *cf;
    604.         struct sk_buff *skb;
    605.         u32 id_rockchip_canfd, dlc;
    606.         int i = 0;
    607.         u32 __maybe_unused ts, ret;
    608.         u32 data[16] = {0};
    610.         dlc = rockchip_canfd_read(rcan, CAN_RXFRD);
    611.         id_rockchip_canfd = rockchip_canfd_read(rcan, CAN_RXFRD);
    612.         ts = rockchip_canfd_read(rcan, CAN_RXFRD);
    613.         for (i = 0; i < 16; i++)
    614.                 data[i] = rockchip_canfd_read(rcan, CAN_RXFRD);
    616.         if (rcan->mode >= ROCKCHIP_CAN_MODE) {
    617.                 /* may be an empty frame */
    618.                 if (!dlc && !id_rockchip_canfd)
    619.                         return 1;
    621.                 if (rcan->txtorx) {
    622.                         if (rockchip_canfd_read(rcan, CAN_TX_CHECK_FIC) & FORMAT_MASK) {
    623.                                 ret = rockchip_canfd_read(rcan, CAN_TXID) & CAN_SFF_MASK;
    624.                                 if ((id_rockchip_canfd == ret) && !(dlc & FORMAT_MASK)) {
    625.                                         rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC,
    626.                                                              ts | CAN_TX0_REQ);
    627.                                         return 1;
    628.                                 } else {
    629.                                         return 1;
    630.                                 }
    631.                         }
    632.                 }
    633.         }
    635.         /* create zero'ed CAN frame buffer */
    636.         if (dlc & FDF_MASK)
    637.                 skb = alloc_canfd_skb(ndev, &cf);
    638.         else
    639.                 skb = alloc_can_skb(ndev, (struct can_frame **)&cf);
    640.         if (!skb) {
    641.                 stats->rx_dropped++;
    642.                 return 1;
    643.         }
    644.  
    645.         /* Change CAN data length format to socketCAN data format */
    646.         if (dlc & FDF_MASK)
    647.                 cf->len = can_dlc2len(dlc & DLC_MASK);
    648.         else
    649.                 cf->len = get_can_dlc(dlc & DLC_MASK);
    650.  
    651.         /* Change CAN ID format to socketCAN ID format */
    652.         if (dlc & FORMAT_MASK) {
    653.                 /* The received frame is an Extended format frame */
    654.                 cf->can_id = id_rockchip_canfd;
    655.                 cf->can_id |= CAN_EFF_FLAG;
    656.                 if (dlc & RTR_MASK)
    657.                         cf->can_id |= CAN_RTR_FLAG;
    658.         } else {
    659.                 /* The received frame is a standard format frame */
    660.                 cf->can_id = id_rockchip_canfd;
    661.                 if (dlc & RTR_MASK)
    662.                         cf->can_id |= CAN_RTR_FLAG;
    663.         }
    664.  
    665.         if (dlc & BRS_MASK)
    666.                 cf->flags |= CANFD_BRS;
    667.  
    668.         if (!(cf->can_id & CAN_RTR_FLAG)) {
    669.                 /* Change CAN data format to socketCAN data format */
    670.                 for (i = 0; i < cf->len; i += 4)
    671.                         *(u32 *)(cf->data + i) = data[i / 4];
    672.         }
    673.  
    674.         stats->rx_packets++;
    675.         stats->rx_bytes += cf->len;
    676.         netif_rx(skb);
    677.  
    678.         can_led_event(ndev, CAN_LED_EVENT_RX);
    679.  
    680.         return 1;
    681. }
    682.  
    683. static int rockchip_canfd_err(struct net_device *ndev, u32 isr)
    684. {
    685.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    686.         struct net_device_stats *stats = &ndev->stats;
    687.         struct can_frame *cf;
    688.         struct sk_buff *skb;
    689.         unsigned int rxerr, txerr;
    690.         u32 sta_reg;
    691.  
    692.         skb = alloc_can_err_skb(ndev, &cf);
    693.  
    694.         rxerr = rockchip_canfd_read(rcan, CAN_RX_ERR_CNT);
    695.         txerr = rockchip_canfd_read(rcan, CAN_TX_ERR_CNT);
    696.         sta_reg = rockchip_canfd_read(rcan, CAN_STATE);
    697.  
    698.         if (skb) {
    699.                 cf->data[6] = txerr;
    700.                 cf->data[7] = rxerr;
    701.         }
    702.  
    703.         if (isr & BUS_OFF_INT) {
    704.                 rcan->can.state = CAN_STATE_BUS_OFF;
    705.                 rcan->can.can_stats.bus_off++;
    706.                 cf->can_id |= CAN_ERR_BUSOFF;
    707.         } else if (isr & ERR_WARN_INT) {
    708.                 rcan->can.can_stats.error_warning++;
    709.                 rcan->can.state = CAN_STATE_ERROR_WARNING;
    710.                 /* error warning state */
    711.                 if (likely(skb)) {
    712.                         cf->can_id |= CAN_ERR_CRTL;
    713.                         cf->data[1] = (txerr > rxerr) ?
    714.                                 CAN_ERR_CRTL_TX_WARNING :
    715.                                 CAN_ERR_CRTL_RX_WARNING;
    716.                         cf->data[6] = txerr;
    717.                         cf->data[7] = rxerr;
    718.                 }
    719.         } else if (isr & PASSIVE_ERR_INT) {
    720.                 rcan->can.can_stats.error_passive++;
    721.                 rcan->can.state = CAN_STATE_ERROR_PASSIVE;
    722.                 /* error passive state */
    723.                 cf->can_id |= CAN_ERR_CRTL;
    724.                 cf->data[1] = (txerr > rxerr) ?
    725.                                         CAN_ERR_CRTL_TX_WARNING :
    726.                                         CAN_ERR_CRTL_RX_WARNING;
    727.                 cf->data[6] = txerr;
    728.                 cf->data[7] = rxerr;
    729.         }
    730.  
    731.         if (rcan->can.state >= CAN_STATE_BUS_OFF ||
    732.             ((sta_reg & 0x20) == 0x20)) {
    733.                 can_bus_off(ndev);
    734.         }
    735.  
    736.         stats->rx_packets++;
    737.         stats->rx_bytes += cf->can_dlc;
    738.         netif_rx(skb);
    739.  
    740.         return 0;
    741. }
    742.  
    743. static irqreturn_t rockchip_canfd_interrupt(int irq, void *dev_id)
    744. {
    745.         struct net_device *ndev = (struct net_device *)dev_id;
    746.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    747.         struct net_device_stats *stats = &ndev->stats;
    748.         u32 err_int = ERR_WARN_INT | RX_BUF_OV_INT | PASSIVE_ERR_INT |
    749.                       TX_LOSTARB_INT | BUS_ERR_INT | BUS_OFF_INT;
    750.         u32 isr;
    751.         u32 dlc = 0;
    752.         u32 quota, work_done = 0;
    753.  
    754.         isr = rockchip_canfd_read(rcan, CAN_INT);
    755.         if (isr & TX_FINISH_INT) {
    756.                 dlc = rockchip_canfd_read(rcan, CAN_TXFIC);
    757.                 /* transmission complete interrupt */
    758.                 if (dlc & FDF_MASK)
    759.                         stats->tx_bytes += can_dlc2len(dlc & DLC_MASK);
    760.                 else
    761.                         stats->tx_bytes += (dlc & DLC_MASK);
    762.                 stats->tx_packets++;
    763.                 if (rcan->txtorx && rcan->mode >= ROCKCHIP_CAN_MODE && dlc & FORMAT_MASK) {
    764.                         cancel_delayed_work(&rcan->tx_err_work);
    765.                         rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC, FORMAT_MASK);
    766.                         do {
    767.                                 quota = (rockchip_canfd_read(rcan, CAN_RXFC) &
    768.                                          rcan->rx_fifo_mask) >>
    769.                                         rcan->rx_fifo_shift;
    770.                         } while (quota == 0); 
    771.                         if (quota) {
    772.                                 while (work_done < quota)
    773.                                         work_done += rockchip_canfd_rx(ndev);
    774.                         }
    775.                         if (rockchip_canfd_read(rcan, CAN_TX_CHECK_FIC) & CAN_TX0_REQ) {
    776.                                 rockchip_canfd_write(rcan, CAN_CMD, CAN_TX1_REQ);
    777.                                 read_poll_timeout_atomic(rockchip_canfd_read, quota,
    778.                                      (quota & 0x3),
    779.                                      0, 5000000, false, rcan, CAN_CMD);
    780.                         }
    781.                         rockchip_canfd_write(rcan, CAN_TX_CHECK_FIC, 0);
    782.                 }
    783.                 rockchip_canfd_write(rcan, CAN_CMD, 0);
    784.                 can_get_echo_skb(ndev, 0);
    785.                 netif_wake_queue(ndev);
    786.                 can_led_event(ndev, CAN_LED_EVENT_TX);
    787.         }
    788.  
    789.         if (isr & RX_FINISH_INT) {
    790.                 quota = (rockchip_canfd_read(rcan, CAN_RXFC) & rcan->rx_fifo_mask) >>
    791.                         rcan->rx_fifo_shift;
    792.                 if (quota) {
    793.                         while (work_done < quota)
    794.                                 work_done += rockchip_canfd_rx(ndev);
    795.                 }
    796.         }
    797.  
    798.         if (isr & err_int) {
    799.                 /* error interrupt */
    800.                 if (rockchip_canfd_err(ndev, isr))
    801.                         netdev_err(ndev, "can't allocate buffer - clearing pending interrupts\n");
    802.         }
    803.  
    804.         rockchip_canfd_write(rcan, CAN_INT, isr);
    805.         return IRQ_HANDLED;
    806. }
    807.  
    808. static int rockchip_canfd_open(struct net_device *ndev)
    809. {
    810.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    811.         int err;
    812.  
    813.         /* common open */
    814.         err = open_candev(ndev);
    815.         if (err)
    816.                 return err;
    817.  
    818.         err = pm_runtime_get_sync(rcan->dev);
    819.         if (err < 0) {
    820.                 netdev_err(ndev, "%s: pm_runtime_get failed(%d)\n",
    821.                            __func__, err);
    822.                 goto exit;
    823.         }
    824.  
    825.         err = rockchip_canfd_start(ndev);
    826.         if (err) {
    827.                 netdev_err(ndev, "could not start CAN peripheral\n");
    828.                 goto exit_can_start;
    829.         }
    830.  
    831.         can_led_event(ndev, CAN_LED_EVENT_OPEN);
    832.         netif_start_queue(ndev);
    833.  
    834.         netdev_dbg(ndev, "%s\n", __func__);
    835.         return 0;
    836.  
    837. exit_can_start:
    838.         pm_runtime_put(rcan->dev);
    839. exit:
    840.         close_candev(ndev);
    841.         return err;
    842. }
    843.  
    844. static int rockchip_canfd_close(struct net_device *ndev)
    845. {
    846.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    847.  
    848.         netif_stop_queue(ndev);
    849.         rockchip_canfd_stop(ndev);
    850.         close_candev(ndev);
    851.         can_led_event(ndev, CAN_LED_EVENT_STOP);
    852.         pm_runtime_put(rcan->dev);
    853.         cancel_delayed_work_sync(&rcan->tx_err_work);
    854.  
    855.         netdev_dbg(ndev, "%s\n", __func__);
    856.         return 0;
    857. }
    858.  
    859. static const struct net_device_ops rockchip_canfd_netdev_ops = {
    860.         .ndo_open = rockchip_canfd_open,
    861.         .ndo_stop = rockchip_canfd_close,
    862.         .ndo_start_xmit = rockchip_canfd_start_xmit,
    863.         .ndo_change_mtu = can_change_mtu,
    864. };
    865.  
    866. /**
    867.  * rockchip_canfd_suspend - Suspend method for the driver
    868.  * @dev:        Address of the device structure
    869.  *
    870.  * Put the driver into low power mode.
    871.  * Return: 0 on success and failure value on error
    872.  */
    873. static int __maybe_unused rockchip_canfd_suspend(struct device *dev)
    874. {
    875.         struct net_device *ndev = dev_get_drvdata(dev);
    876.  
    877.         if (netif_running(ndev)) {
    878.                 netif_stop_queue(ndev);
    879.                 netif_device_detach(ndev);
    880.                 rockchip_canfd_stop(ndev);
    881.         }
    882.  
    883.         return pm_runtime_force_suspend(dev);
    884. }
    885.  
    886. /**
    887.  * rockchip_canfd_resume - Resume from suspend
    888.  * @dev:        Address of the device structure
    889.  *
    890.  * Resume operation after suspend.
    891.  * Return: 0 on success and failure value on error
    892.  */
    893. static int __maybe_unused rockchip_canfd_resume(struct device *dev)
    894. {
    895.         struct net_device *ndev = dev_get_drvdata(dev);
    896.         int ret;
    897.  
    898.         ret = pm_runtime_force_resume(dev);
    899.         if (ret) {
    900.                 dev_err(dev, "pm_runtime_force_resume failed on resume\n");
    901.                 return ret;
    902.         }
    903.  
    904.         if (netif_running(ndev)) {
    905.                 ret = rockchip_canfd_start(ndev);
    906.                 if (ret) {
    907.                         dev_err(dev, "rockchip_canfd_chip_start failed on resume\n");
    908.                         return ret;
    909.                 }
    910.  
    911.                 netif_device_attach(ndev);
    912.                 netif_start_queue(ndev);
    913.         }
    914.  
    915.         return 0;
    916. }
    917.  
    918. /**
    919.  * rockchip_canfd_runtime_suspend - Runtime suspend method for the driver
    920.  * @dev:        Address of the device structure
    921.  *
    922.  * Put the driver into low power mode.
    923.  * Return: 0 always
    924.  */
    925. static int __maybe_unused rockchip_canfd_runtime_suspend(struct device *dev)
    926. {
    927.         struct net_device *ndev = dev_get_drvdata(dev);
    928.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    929.  
    930.         clk_bulk_disable_unprepare(rcan->num_clks, rcan->clks);
    931.  
    932.         return 0;
    933. }
    934.  
    935. /**
    936.  * rockchip_canfd_runtime_resume - Runtime resume from suspend
    937.  * @dev:        Address of the device structure
    938.  *
    939.  * Resume operation after suspend.
    940.  * Return: 0 on success and failure value on error
    941.  */
    942. static int __maybe_unused rockchip_canfd_runtime_resume(struct device *dev)
    943. {
    944.         struct net_device *ndev = dev_get_drvdata(dev);
    945.         struct rockchip_canfd *rcan = netdev_priv(ndev);
    946.         int ret;
    947.  
    948.         ret = clk_bulk_prepare_enable(rcan->num_clks, rcan->clks);
    949.         if (ret) {
    950.                 dev_err(dev, "Cannot enable clock.\n");
    951.                 return ret;
    952.         }
    953.  
    954.         return 0;
    955. }
    956.  
    957. static const struct dev_pm_ops rockchip_canfd_dev_pm_ops = {
    958.         SET_SYSTEM_SLEEP_PM_OPS(rockchip_canfd_suspend, rockchip_canfd_resume)
    959.         SET_RUNTIME_PM_OPS(rockchip_canfd_runtime_suspend,
    960.                            rockchip_canfd_runtime_resume, NULL)
    961. };
    962.  
    963. static const struct of_device_id rockchip_canfd_of_match[] = {
    964.         {
    965.                 .compatible = "rockchip,canfd-1.0",
    966.                 .data = (void *)ROCKCHIP_CANFD_MODE
    967.         },
    968.         {
    969.                 .compatible = "rockchip,can-2.0",
    970.                 .data = (void *)ROCKCHIP_CAN_MODE
    971.         },
    972.         {
    973.                 .compatible = "rockchip,rk3568-can-2.0",
    974.                 .data = (void *)ROCKCHIP_RK3568_CAN_MODE
    975.         },
    976.         {},
    977. };
    978. MODULE_DEVICE_TABLE(of, rockchip_canfd_of_match);
    979.  
    980. static int rockchip_canfd_probe(struct platform_device *pdev)
    981. {
    982.         struct net_device *ndev;
    983.         struct rockchip_canfd *rcan;
    984.         struct resource *res;
    985.         void __iomem *addr;
    986.         int err, irq;
    987.  
    988.         irq = platform_get_irq(pdev, 0);
    989.         if (irq < 0) {
    990.                 dev_err(&pdev->dev, "could not get a valid irq\n");
    991.                 return -ENODEV;
    992.         }
    993.  
    994.         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
    995.         addr = devm_ioremap_resource(&pdev->dev, res);
    996.         if (IS_ERR(addr))
    997.                 return -EBUSY;
    998.  
    999.         ndev = alloc_candev(sizeof(struct rockchip_canfd), 1);
    1000.         if (!ndev) {
    1001.                 dev_err(&pdev->dev, "could not allocate memory for CANFD device\n");
    1002.                 return -ENOMEM;
    1003.         }
    1004.         rcan = netdev_priv(ndev);
    1005.  
    1006.         /* register interrupt handler */
    1007.         err = devm_request_irq(&pdev->dev, irq, rockchip_canfd_interrupt,
    1008.                                0, ndev->name, ndev);
    1009.         if (err) {
    1010.                 dev_err(&pdev->dev, "request_irq err: %d\n", err);
    1011.                 return err;
    1012.         }
    1013.  
    1014.         rcan->reset = devm_reset_control_array_get(&pdev->dev, false, false);
    1015.         if (IS_ERR(rcan->reset)) {
    1016.                 if (PTR_ERR(rcan->reset) != -EPROBE_DEFER)
    1017.                         dev_err(&pdev->dev, "failed to get canfd reset lines\n");
    1018.                 return PTR_ERR(rcan->reset);
    1019.         }
    1020.         rcan->num_clks = devm_clk_bulk_get_all(&pdev->dev, &rcan->clks);
    1021.         if (rcan->num_clks < 1)
    1022.                 return -ENODEV;
    1023.  
    1024.         rcan->mode = (unsigned long)of_device_get_match_data(&pdev->dev);
    1025.  
    1026.         rcan->base = addr;
    1027.         rcan->can.clock.freq = clk_get_rate(rcan->clks[0].clk);
    1028.         rcan->dev = &pdev->dev;
    1029.         rcan->can.state = CAN_STATE_STOPPED;
    1030.         switch (rcan->mode) {
    1031.         case ROCKCHIP_CANFD_MODE:
    1032.                 rcan->can.bittiming_const = &rockchip_canfd_bittiming_const;
    1033.                 rcan->can.data_bittiming_const = &rockchip_canfd_data_bittiming_const;
    1034.                 rcan->can.do_set_mode = rockchip_canfd_set_mode;
    1035.                 rcan->can.do_get_berr_counter = rockchip_canfd_get_berr_counter;
    1036.                 rcan->can.do_set_bittiming = rockchip_canfd_set_bittiming;
    1037.                 rcan->can.do_set_data_bittiming = rockchip_canfd_set_bittiming;
    1038.                 rcan->can.ctrlmode = CAN_CTRLMODE_FD;
    1039.                 /* IFI CANFD can do both Bosch FD and ISO FD */
    1040.                 rcan->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
    1041.                                                CAN_CTRLMODE_FD;
    1042.                 rcan->rx_fifo_shift = RX_FIFO_CNT0_SHIFT;
    1043.                 rcan->rx_fifo_mask = RX_FIFO_CNT0_MASK;
    1044.                 break;
    1045.         case ROCKCHIP_CAN_MODE:
    1046.         case ROCKCHIP_RK3568_CAN_MODE:
    1047.                 rcan->can.bittiming_const = &rockchip_canfd_bittiming_const;
    1048.                 rcan->can.do_set_mode = rockchip_canfd_set_mode;
    1049.                 rcan->can.do_get_berr_counter = rockchip_canfd_get_berr_counter;
    1050.                 rcan->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING |
    1051.                                                CAN_CTRLMODE_LISTENONLY |
    1052.                                                CAN_CTRLMODE_LOOPBACK |
    1053.                                                CAN_CTRLMODE_3_SAMPLES;
    1054.                 rcan->rx_fifo_shift = RX_FIFO_CNT0_SHIFT;
    1055.                 rcan->rx_fifo_mask = RX_FIFO_CNT0_MASK;
    1056.                 break;
    1057.         default:
    1058.                 return -EINVAL;
    1059.         }
    1060.  
    1061.         if (rcan->mode == ROCKCHIP_CAN_MODE) {
    1062.                 rcan->rx_fifo_shift = RX_FIFO_CNT1_SHIFT;
    1063.                 rcan->rx_fifo_mask = RX_FIFO_CNT1_MASK;
    1064.         }
    1065.  
    1066.         if (device_property_read_u32_array(&pdev->dev,
    1067.                                            "rockchip,tx-invalid-info",
    1068.                                            rcan->tx_invalid, 4))
    1069.                 rcan->txtorx = 1;
    1070.  
    1071.         ndev->netdev_ops = &rockchip_canfd_netdev_ops;
    1072.         ndev->irq = irq;
    1073.         ndev->flags |= IFF_ECHO;
    1074.         rcan->can.restart_ms = 1;
    1075.  
    1076.         INIT_DELAYED_WORK(&rcan->tx_err_work, rockchip_canfd_tx_err_delay_work);
    1077.  
    1078.         platform_set_drvdata(pdev, ndev);
    1079.         SET_NETDEV_DEV(ndev, &pdev->dev);
    1080.  
    1081.         pm_runtime_enable(&pdev->dev);
    1082.         err = pm_runtime_get_sync(&pdev->dev);
    1083.         if (err < 0) {
    1084.                 dev_err(&pdev->dev, "%s: pm_runtime_get failed(%d)\n",
    1085.                         __func__, err);
    1086.                 goto err_pmdisable;
    1087.         }
    1088.  
    1089.         err = register_candev(ndev);
    1090.         if (err) {
    1091.                 dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
    1092.                         DRV_NAME, err);
    1093.                 goto err_disableclks;
    1094.         }
    1095.  
    1096.         devm_can_led_init(ndev);
    1097.  
    1098.         return 0;
    1099.  
    1100. err_disableclks:
    1101.         pm_runtime_put(&pdev->dev);
    1102. err_pmdisable:
    1103.         pm_runtime_disable(&pdev->dev);
    1104.         free_candev(ndev);
    1105.  
    1106.         return err;
    1107. }
    1108.  
    1109. static int rockchip_canfd_remove(struct platform_device *pdev)
    1110. {
    1111.         struct net_device *ndev = platform_get_drvdata(pdev);
    1112.  
    1113.         unregister_netdev(ndev);
    1114.         pm_runtime_disable(&pdev->dev);
    1115.         free_candev(ndev);
    1116.  
    1117.         return 0;
    1118. }
    1119.  
    1120. static struct platform_driver rockchip_canfd_driver = {
    1121.         .driver = {
    1122.                 .name = DRV_NAME,
    1123.                 .pm = &rockchip_canfd_dev_pm_ops,
    1124.                 .of_match_table = rockchip_canfd_of_match,
    1125.         },
    1126.         .probe = rockchip_canfd_probe,
    1127.         .remove = rockchip_canfd_remove,
    1128. };
    1129. module_platform_driver(rockchip_canfd_driver);
    1130.  
    1131. MODULE_AUTHOR("Elaine Zhang ");
    1132. MODULE_LICENSE("GPL");
    1133. MODULE_DESCRIPTION("Rockchip CANFD Drivers");

    【iopoll.h】 
    1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. /*
    3.  * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
    4.  */
    5.  
    6. #ifndef _LINUX_IOPOLL_H
    7. #define _LINUX_IOPOLL_H
    8.  
    9. #include <linux/kernel.h>
    10. #include <linux/types.h>
    11. #include <linux/ktime.h>
    12. #include <linux/delay.h>
    13. #include <linux/errno.h>
    14. #include <linux/io.h>
    15.  
    16. /**
    17.  * read_poll_timeout - Periodically poll an address until a condition is
    18.  *                      met or a timeout occurs
    19.  * @op: accessor function (takes @args as its arguments)
    20.  * @val: Variable to read the value into
    21.  * @cond: Break condition (usually involving @val)
    22.  * @sleep_us: Maximum time to sleep between reads in us (0
    23.  *            tight-loops).  Should be less than ~20ms since usleep_range
    24.  *            is used (see Documentation/timers/timers-howto.rst).
    25.  * @timeout_us: Timeout in us, 0 means never timeout
    26.  * @sleep_before_read: if it is true, sleep @sleep_us before read.
    27.  * @args: arguments for @op poll
    28.  *
    29.  * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
    30.  * case, the last read value at @args is stored in @val. Must not
    31.  * be called from atomic context if sleep_us or timeout_us are used.
    32.  *
    33.  * When available, you'll probably want to use one of the specialized
    34.  * macros defined below rather than this macro directly.
    35.  */
    36. #define read_poll_timeout(op, val, cond, sleep_us, timeout_us, \
    37.                                 sleep_before_read, args...) \
    38. ({ \
    39.         u64 __timeout_us = (timeout_us); \
    40.         unsigned long __sleep_us = (sleep_us); \
    41.         ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
    42.         might_sleep_if((__sleep_us) != 0); \
    43.         if (sleep_before_read && __sleep_us) \
    44.                 usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
    45.         for (;;) { \
    46.                 (val) = op(args); \
    47.                 if (cond) \
    48.                         break; \
    49.                 if (__timeout_us && \
    50.                     ktime_compare(ktime_get(), __timeout) > 0) { \
    51.                         (val) = op(args); \
    52.                         break; \
    53.                 } \
    54.                 if (__sleep_us) \
    55.                         usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
    56.         } \
    57.         (cond) ? 0 : -ETIMEDOUT; \
    58. })
    60. /**
    61.  * read_poll_timeout_atomic - Periodically poll an address until a condition is
    62.  *                              met or a timeout occurs
    63.  * @op: accessor function (takes @args as its arguments)
    64.  * @val: Variable to read the value into
    65.  * @cond: Break condition (usually involving @val)
    66.  * @delay_us: Time to udelay between reads in us (0 tight-loops).  Should
    67.  *            be less than ~10us since udelay is used (see
    68.  *            Documentation/timers/timers-howto.rst).
    69.  * @timeout_us: Timeout in us, 0 means never timeout
    70.  * @delay_before_read: if it is true, delay @delay_us before read.
    71.  * @args: arguments for @op poll
    72.  *
    73.  * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
    74.  * case, the last read value at @args is stored in @val.
    75.  *
    76.  * When available, you'll probably want to use one of the specialized
    77.  * macros defined below rather than this macro directly.
    78.  */
    79. #define read_poll_timeout_atomic(op, val, cond, delay_us, timeout_us, \
    80.                                         delay_before_read, args...) \
    81. ({ \
    82.         u64 __timeout_us = (timeout_us); \
    83.         unsigned long __delay_us = (delay_us); \
    84.         ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
    85.         if (delay_before_read && __delay_us) \
    86.                 udelay(__delay_us); \
    87.         for (;;) { \
    88.                 (val) = op(args); \
    89.                 if (cond) \
    90.                         break; \
    91.                 if (__timeout_us && \
    92.                     ktime_compare(ktime_get(), __timeout) > 0) { \
    93.                         (val) = op(args); \
    94.                         break; \
    95.                 } \
    96.                 if (__delay_us) \
    97.                         udelay(__delay_us); \
    98.         } \
    99.         (cond) ? 0 : -ETIMEDOUT; \
    100. })
    101.  
    102. /**
    103.  * readx_poll_timeout - Periodically poll an address until a condition is met or a timeout occurs
    104.  * @op: accessor function (takes @addr as its only argument)
    105.  * @addr: Address to poll
    106.  * @val: Variable to read the value into
    107.  * @cond: Break condition (usually involving @val)
    108.  * @sleep_us: Maximum time to sleep between reads in us (0
    109.  *            tight-loops).  Should be less than ~20ms since usleep_range
    110.  *            is used (see Documentation/timers/timers-howto.rst).
    111.  * @timeout_us: Timeout in us, 0 means never timeout
    112.  *
    113.  * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
    114.  * case, the last read value at @addr is stored in @val. Must not
    115.  * be called from atomic context if sleep_us or timeout_us are used.
    116.  *
    117.  * When available, you'll probably want to use one of the specialized
    118.  * macros defined below rather than this macro directly.
    119.  */
    120. #define readx_poll_timeout(op, addr, val, cond, sleep_us, timeout_us)   \
    121.         read_poll_timeout(op, val, cond, sleep_us, timeout_us, false, addr)
    123. /**
    124.  * readx_poll_timeout_atomic - Periodically poll an address until a condition is met or a timeout occurs
    125.  * @op: accessor function (takes @addr as its only argument)
    126.  * @addr: Address to poll
    127.  * @val: Variable to read the value into
    128.  * @cond: Break condition (usually involving @val)
    129.  * @delay_us: Time to udelay between reads in us (0 tight-loops).  Should
    130.  *            be less than ~10us since udelay is used (see
    131.  *            Documentation/timers/timers-howto.rst).
    132.  * @timeout_us: Timeout in us, 0 means never timeout
    133.  *
    134.  * Returns 0 on success and -ETIMEDOUT upon a timeout. In either
    135.  * case, the last read value at @addr is stored in @val.
    136.  *
    137.  * When available, you'll probably want to use one of the specialized
    138.  * macros defined below rather than this macro directly.
    139.  */
    140. #define readx_poll_timeout_atomic(op, addr, val, cond, delay_us, timeout_us) \
    141.         read_poll_timeout_atomic(op, val, cond, delay_us, timeout_us, false, addr)
    142.  
    143. #define readb_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    144.         readx_poll_timeout(readb, addr, val, cond, delay_us, timeout_us)
    145.  
    146. #define readb_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    147.         readx_poll_timeout_atomic(readb, addr, val, cond, delay_us, timeout_us)
    148.  
    149. #define readw_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    150.         readx_poll_timeout(readw, addr, val, cond, delay_us, timeout_us)
    151.  
    152. #define readw_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    153.         readx_poll_timeout_atomic(readw, addr, val, cond, delay_us, timeout_us)
    154.  
    155. #define readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    156.         readx_poll_timeout(readl, addr, val, cond, delay_us, timeout_us)
    157.  
    158. #define readl_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    159.         readx_poll_timeout_atomic(readl, addr, val, cond, delay_us, timeout_us)
    160.  
    161. #define readq_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    162.         readx_poll_timeout(readq, addr, val, cond, delay_us, timeout_us)
    163.  
    164. #define readq_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    165.         readx_poll_timeout_atomic(readq, addr, val, cond, delay_us, timeout_us)
    166.  
    167. #define readb_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    168.         readx_poll_timeout(readb_relaxed, addr, val, cond, delay_us, timeout_us)
    169.  
    170. #define readb_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    171.         readx_poll_timeout_atomic(readb_relaxed, addr, val, cond, delay_us, timeout_us)
    172.  
    173. #define readw_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    174.         readx_poll_timeout(readw_relaxed, addr, val, cond, delay_us, timeout_us)
    175.  
    176. #define readw_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    177.         readx_poll_timeout_atomic(readw_relaxed, addr, val, cond, delay_us, timeout_us)
    178.  
    179. #define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    180.         readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us)
    181.  
    182. #define readl_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    183.         readx_poll_timeout_atomic(readl_relaxed, addr, val, cond, delay_us, timeout_us)
    184.  
    185. #define readq_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \
    186.         readx_poll_timeout(readq_relaxed, addr, val, cond, delay_us, timeout_us)
    187.  
    188. #define readq_relaxed_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) \
    189.         readx_poll_timeout_atomic(readq_relaxed, addr, val, cond, delay_us, timeout_us)
    190.  
    191. #endif /* _LINUX_IOPOLL_H */

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  • 原文地址：https://blog.csdn.net/weixin_55163060/article/details/132879875