• Design Compiler工具学习笔记（6）

    目录

    引言

    知识储备

    实际操作

    设计源码

    仿真源码

    VCS执行仿真

    DC 综合

    TCL编程练习

    引言

    本篇继续学习 DC的基本使用。本篇主要学习 DC 综合之后的效果分析，重点在时序分析。

    前文链接：

    Design Compiler工具学习笔记（1）

    Design Compiler工具学习笔记（2）

    Design Compiler工具学习笔记（3）

    Design Compiler工具学习笔记（4）

    Design Compiler工具学习笔记（5）

    知识储备

     小数点精度位数一般为 13 （-significant_digits）

     report_timing :：仅报告最差的路径时序；

    report_timing -max_paths 2 ：报告出两条最差的路径，但是这两条路径的终点不同

    report_timing -nworst 2 -max_paths 2：报告出整个设计中最差的两条路径，可以是同一个终点

     建立时间违规必须全部修改，面积违规和保持时间违规可以保留。

    出现违规时可能的情况：输入/出延迟过大，约束过紧；设计的组合逻辑部分延迟过大。

     

     

     

     

     

     

     

     

     

     

     

    实际操作

    以单比特信号以握手方式完成时钟域跨越。

    设计源码

    1. // |===================================== TOP ==============================
    2. // |Author:Xu Y. B.
    3. // |Date:2022-11-23
    4. // |Description: TOP module 
    5. // |			 about single bit signal CDC using handshake mode
    6. // |			 CDC:100MHz-->50MHz
    7. // |========================================================================
    8.  
    9. module TOP (
    10. // ======================= module input ports specify ================== 
    11. // time domain 100MHz
    12. input 						I_CLK_100M,
    13. input 						I_RSTN_100M,
    14.  
    15.  
    16. // time domain 200MHz
    17. input 						I_CLK_50M,
    18. input 						I_RSTN_50M,
    19.  
    20. // operate enable
    21. input 						I_OPR_EN,//high,start 1 CDC test
    22.  
    23. // ======================= module output ports specify ================== 
    24. output 		reg 			O_CDC_DONE
    25.  
    26. );
    27. // ======================= module local parameters =====================
    28.  
    29.  
    30. // ======================= module internal signals =====================
    31. // register input signal I_OPR_EN  
    32. reg 						[1:0]				R_I_OPR_EN;
    33. wire 											W_I_OPR_EN_PDG;
    34. reg 											R_CDC_QST_100M;
    35. reg 						[1:0]				R_CDC_QST_50M;
    36.  
    37. reg 											R_CDC_ACK_50M;
    38. reg 						[1:0]				R_CDC_ACK_100M;
    39.  
    40. // ======================= module design logic =========================
    41. always @ (posedge I_CLK_100M)
    42. begin:pro_opr_en_reg
    43. 	if(~I_RSTN_100M)
    44. 	begin
    45. 		R_I_OPR_EN <= 2'b00;
    46. 	end
    47. 	else
    48. 	begin
    49. 		R_I_OPR_EN[0] <= I_OPR_EN;
    50. 		R_I_OPR_EN[1] <= R_I_OPR_EN[0];
    51. 	end
    52. end
    54. assign W_I_OPR_EN_PDG = R_I_OPR_EN[0] & (~R_I_OPR_EN[1]);
    56. always @ (posedge I_CLK_100M)
    57. begin
    58. 	if(~I_RSTN_100M)
    59. 	begin
    60. 		R_CDC_QST_100M <= 0;
    61. 	end
    62. 	else
    63. 	begin
    64. 		if(W_I_OPR_EN_PDG)
    65. 		begin
    66. 			R_CDC_QST_100M <= 1;
    67. 		end
    68. 		else if(R_CDC_ACK_100M[1])
    69. 		begin
    70. 			R_CDC_QST_100M <= 0;
    71. 		end
    72. 		else
    73. 		begin
    74. 			R_CDC_QST_100M <= R_CDC_QST_100M;
    75. 		end
    76. 	end
    77. end
    79. always @ (posedge I_CLK_100M)
    80. begin
    81. 	if(~I_RSTN_100M)
    82. 	begin
    83. 		R_CDC_ACK_100M <=2'b0;
    84. 	end
    85. 	else
    86. 	begin
    87. 		R_CDC_ACK_100M[0] <= R_CDC_ACK_50M;
    88. 		R_CDC_ACK_100M[1] <= R_CDC_ACK_100M[0];
    89. 	end
    90. end
    91.  
    92. // 50M
    93. always @ (posedge I_CLK_50M)
    94. begin
    95. 	if(~I_RSTN_50M)
    96. 	begin
    97. 		R_CDC_ACK_50M <= 0;
    98. 	end
    99. 	else
    100. 	begin
    101. 		if(R_CDC_QST_50M[1])
    102. 		begin
    103. 			R_CDC_ACK_50M <= 1;
    104. 		end
    105. 		else
    106. 		begin
    107. 			R_CDC_ACK_50M <= 0;
    108. 		end
    109. 	end
    110. end
    111.  
    112. always @ (posedge I_CLK_50M)
    113. begin
    114. 	if(~I_RSTN_50M)
    115. 	begin
    116. 		R_CDC_QST_50M <= 2'b00;
    117. 	end
    118. 	else
    119. 	begin
    120. 		R_CDC_QST_50M[0] <= R_CDC_QST_100M;
    121. 		R_CDC_QST_50M[1] <= R_CDC_QST_50M[0];
    122. 	end
    123. end
    125. always @ (posedge I_CLK_100M)
    126. begin
    127. 	if(~I_RSTN_100M)
    128. 	begin
    129. 		O_CDC_DONE <= 0;
    130. 	end
    131. 	else
    132. 	begin
    133. 		if(R_CDC_ACK_100M)
    134. 		begin
    135. 			O_CDC_DONE <= 1;
    136. 		end
    137. 		else
    138. 		begin
    139. 			O_CDC_DONE <= 0;
    140. 		end
    141. 	end
    142. end
    146. endmodule

    仿真源码

    1. // |========================== Test Bench ===========================
    2. // |Author:Xu Y. B.
    3. // |Date:2022-11-23
    4. // |Description: TOP module 
    5. // |			 about single bit signal CDC using handshake mode
    6. // |			 CDC:100MHz-->50MHz
    7. // |			 Test Bench
    8. // |==================================================================
    9.  
    10.  
    11. module TB ();
    12.  
    13. // time domain 100MHz
    14. reg 						I_CLK_100M;
    15. reg 						I_RSTN_100M;
    16.  
    17.  
    18. // time domain 200MHz
    19. reg 						I_CLK_50M;
    20. reg 						I_RSTN_50M;
    21.  
    22. // operate enable
    23. reg 						I_OPR_EN;//high,start 1 CDC test
    24.  
    25. // ======================= module output ports specify ================== 
    26. wire			 			O_CDC_DONE;
    27.  
    28.  
    29. // ======================= generate clocks ==============================
    30. initial I_CLK_100M = 0;
    31. always #5 I_CLK_100M = ~I_CLK_100M;
    32.  
    33. initial I_CLK_50M = 0;
    34. always #10 I_CLK_50M = ~I_CLK_50M;
    35.  
    36. initial
    37. begin
    38. 	I_RSTN_100M = 0;
    39. 	I_RSTN_50M = 0;
    40. 	I_OPR_EN = 0;
    41. 	#20;
    42. 	I_RSTN_100M = 1;
    43. 	#40;
    44. 	I_RSTN_50M = 1;
    45. 	#20;
    46. 	I_OPR_EN = 1;
    47.  
    48. 	@(negedge O_CDC_DONE)
    49. 	#50;
    50. 	$finish;
    51. end
    52.  
    53. initial
    54. begin
    55. 	`ifdef VPD_TEST
    56. 		$vcdpluson();
    57. 	`endif
    58. end
    59.  
    60. TOP INST_TOP
    61. 	(
    62. 		.I_CLK_100M  (I_CLK_100M),
    63. 		.I_RSTN_100M (I_RSTN_100M),
    64. 		.I_CLK_50M   (I_CLK_50M),
    65. 		.I_RSTN_50M  (I_RSTN_50M),
    66. 		.I_OPR_EN    (I_OPR_EN),
    67. 		.O_CDC_DONE  (O_CDC_DONE)
    68. 	);
    69.  
    70.  
    71. endmodule

    VCS执行仿真

    makefile 文件：

    1. # =======================================================
    2. # ========================== MAKE FILE ==================
    3. # By:Xu Y. B.
    4. # Date:2022-11-23
    5. # Note:
    6. # reuse this makefile ,the followings should be changed:
    7. # -1- OUTPUT
    8. # -2- TB file add the following:
    9. # 	  `ifdef VPD_TEST
    10. # 			$vcdpluson();
    11. # 	  `endif
    12. # =======================================================
    13.  
    14. .PHONY: com cov clean debug
    15.  
    16. OUTPUT = SIMV_CDC_TEST
    17.  
    18. VPD_SW_DEFINE = +define+VPD_TEST
    19.  
    20.  
    21. # code coverage command
    22. CM = -cm line+cond+fsm+branch+tgl
    23. CM_NAME = -cm_name $(OUTPUT)
    24. CM_DIR = -cm_dir ./$(OUTPUT).vdb
    25.  
    26. # vpdfile name
    27. VPD_NAME = $(OUTPUT).vpd
    28.  
    29.  
    30. # compile command
    31. VCS = vcs -full64 -cpp g++-4.8 -cc gcc-4.8 -LDFLAGS -Wl,--no-as-needed   \
    32. 	  -simprofile 							 \
    33. 	  -sverilog +v2k -timescale=1ns/1ns      \
    34.       -debug_access+r 	             		 \
    35.       -Mupdate								 \
    36.       +notimingcheck			     		 \
    37.       +nospecify			                 \
    38.       +vcs+flush+all			             \
    39.       $(VPD_SW_DEFINE)						 \
    40.       -o $(OUTPUT)							 \
    41.       -l compile.log						 
    42.       # $(CM)				                 	 \
    43.       # $(CM_NAME)							 \
    44.       # $(CM_DIR)								 
    45. # -cm_hier ./vcs_cov.cfg
    46.       							 
    47.       
    48.  
    49. # simulation command
    50. SIM = ./$(OUTPUT)							 \
    51.       -l $(OUTPUT).log						 \
    52. 	  $(CM) $(CM_NAME) $(CM_DIR)	         \
    53. 	  $(VPD_NAME)							 \
    54. 	  
    55.  
    56. # start complie
    57. com:	
    58. 	find -name "*.v" >filelist.f 
    59. 	$(VCS) -f filelist.f
    60.  
    61.  
    62. # start simulation
    63. sim:
    64. 	$(SIM)
    65. 	mv vcdplus.vpd $(VPD_NAME)
    66.  
    67. # show the coverage
    68. cov:
    69. 	dve -full64 -covdir *.vdb &
    70. debug:
    71. 	dve -full64 -vpd $(OUTPUT).vpd &
    72.  
    73. # start clean
    74. clean:
    75. 	rm -rf ./csrc *.daidir *.log *.vpd *.vdb simv* *.key *race.out* *.so.* *profile* *.f

    DC 综合

    脚本：

    供参考~~~~~~~~~~

    1. # |===========================================================
    2. # | Author 		: Xu Y. B.
    3. # | Date   		: 2022-11-21
    4. # | Description : tcl script for top design 
    5. # |===========================================================
    6.  
    7.  
    8. # |===========================================================
    9. # |STEP 1: Read & elaborate the RTL design file list & check
    10. # |===========================================================
    11. set TOP_MODULE CDC_TOP
    12. analyze        -format verilog [list CDC_TOP.v ]
    13. elaborate      $TOP_MODULE     -architecture verilog
    14. current_design $TOP_MODULE
    15.  
    16. if {[link] == 0} {
    17. 	echo "Your Link has errors !";
    18. 	exit;
    19. }
    20.  
    21. if {[check_design] == 0} {
    22. 	echo "Your check design has errors !";
    23. 	exit;
    24. }
    25.  
    26. # |===========================================================
    27. # |STEP 2: reset design
    28. # |===========================================================
    29. reset_design
    30.  
    31.  
    32. # |===========================================================
    33. # |STEP 3: Write unmapped ddc file
    34. # |===========================================================
    35. uniquify
    36. set uniquify_naming_style "%s_%d"
    37. write -f ddc -hierarchy -output ${UNMAPPED_PATH}/${TOP_MODULE}.ddc
    38.  
    39.  
    40. # |===========================================================
    41. # |STEP 4: define clocks
    42. # |===========================================================
    43. # -------------------------- CLK 100MHz ----------------------
    44. set       CLK_NAME          	I_CLK_100M
    45. set       CLK_PERIOD        	10
    46. set       CLK_SKEW	        	[expr {$CLK_PERIOD*0.05}]						
    47. set       CLK_TRANS         	[expr {$CLK_PERIOD*0.01}]						
    48. set       CLK_SRC_LATENCY   	[expr {$CLK_PERIOD*0.1 }]						
    49. set       CLK_LATENCY       	[expr {$CLK_PERIOD*0.1 }]						
    50.  
    51. create_clock 			-period 	$CLK_PERIOD  	  [get_ports $CLK_NAME]
    52. set_ideal_network 						 			  [get_ports $CLK_NAME]
    53. set_dont_touch_network 					 			  [get_ports $CLK_NAME]
    54. set_drive 				0 							  [get_ports $CLK_NAME]
    55.  
    56. set_clock_uncertainty   -setup       $CLK_SKEW        [get_clocks $CLK_NAME]
    57. set_clock_transition    -max         $CLK_TRANS       [get_clocks $CLK_NAME]
    58. set_clock_latency       -source -max $CLK_SRC_LATENCY [get_clocks $CLK_NAME]
    59. set_clock_latency       -max         $CLK_LATENCY     [get_clocks $CLK_NAME]
    60.  
    61. # --------------------------- CLK 50MHz ----------------------
    62. set       CLK_NAME_2          	I_CLK_50M
    63. set       CLK_PERIOD_2        	20
    64. set       CLK_SKEW_2	        [expr {$CLK_PERIOD_2*0.05}]						
    65. set       CLK_TRANS_2         	[expr {$CLK_PERIOD_2*0.01}]						
    66. set       CLK_SRC_LATENCY_2   	[expr {$CLK_PERIOD_2*0.1 }]						
    67. set       CLK_LATENCY_2       	[expr {$CLK_PERIOD_2*0.1 }]						
    68.  
    69. create_clock 			-period 	$CLK_PERIOD_2  	  [get_ports $CLK_NAME_2]
    70. set_ideal_network 						 			  [get_ports $CLK_NAME_2]
    71. set_dont_touch_network 					 			  [get_ports $CLK_NAME_2]
    72. set_drive 				0 							  [get_ports $CLK_NAME_2]
    73.  
    74. set_clock_uncertainty   -setup       $CLK_SKEW_2        [get_clocks $CLK_NAME_2]
    75. set_clock_transition    -max         $CLK_TRANS_2       [get_clocks $CLK_NAME_2]
    76. set_clock_latency       -source -max $CLK_SRC_LATENCY_2 [get_clocks $CLK_NAME_2]
    77. set_clock_latency       -max         $CLK_LATENCY_2     [get_clocks $CLK_NAME_2]
    78.  
    79.  
    80. # |===========================================================
    81. # |STEP 5: define reset
    82. # |===========================================================
    83. # ------------------------- RST 1 ----------------------------
    84. set RST_NAME 					I_RSTN_100M
    85. set_ideal_network 				[get_ports $RST_NAME]
    86. set_dont_touch_network          [get_ports $RST_NAME]
    87. set_drive             0         [get_ports $RST_NAME]
    88.  
    89. # ------------------------- RST 2 ----------------------------
    90. set RST_NAME_2 					I_RSTN_50M
    91. set_ideal_network 				[get_ports $RST_NAME_2]
    92. set_dont_touch_network          [get_ports $RST_NAME_2]
    93. set_drive             0         [get_ports $RST_NAME_2]
    94.  
    95.  
    96. # |===========================================================
    97. # |STEP 6: set input delay using timing budget
    98. # |Assume a weak cell to drive the input pins
    99. # |===========================================================
    100. set 		LIB_NAME 			typical
    101. set 		WIRE_LOAD_MODEL 	smic18_wl10
    102. set 		DRIVE_CELL 			INVX1
    103. set 		DRIVE_CELL_2 		INVX4
    104. set 		DRIVE_CELL_3		INVX8
    105.  
    106. set 		DRIVE_PIN 			Y
    107. set 		OPERATE_CONDITION   typical
    108.  
    109. set 		INPUT_RST 			 [get_ports I_RSTN_100M]
    110. set 		INPUT_RST_2			 [get_ports I_RSTN_50M]
    111.  
    112.  
    113. set         INPUT_DELAY 		 [expr {$CLK_PERIOD*0.6}]
    114. set         INPUT_DELAY_2 		 [expr {$CLK_PERIOD_2*0.6}]
    115. # CLK 1
    116. set_input_delay $INPUT_DELAY -clock $CLK_NAME [get_ports I_OPR_EN]
    117. set_input_delay $INPUT_DELAY -clock $CLK_NAME ${INPUT_RST}
    118.  
    119. # CLK 2
    120. set_input_delay $INPUT_DELAY_2 -clock $CLK_NAME_2 ${INPUT_RST_2}
    121.  
    122. # DRIVE CELL
    123. set_driving_cell -lib_cell ${DRIVE_CELL}   -pin ${DRIVE_PIN}   ${INPUT_RST}
    124. set_driving_cell -lib_cell ${DRIVE_CELL_2} -pin ${DRIVE_PIN}   ${INPUT_RST_2}
    125. set_driving_cell -lib_cell ${DRIVE_CELL_3} -pin ${DRIVE_PIN}   [get_ports I_OPR_EN]
    126.  
    127.  
    128.  
    129. # |===========================================================
    130. # |STEP 7: set output delay 
    131. # |===========================================================
    132. set OUTPUT_DELAY  [expr {$CLK_PERIOD*0.6}]
    133. set MAX_LOAD      [expr {[load_of $LIB_NAME/INVX4/A] * 10}]
    134.  
    135. set_output_delay  $OUTPUT_DELAY -clock $CLK_NAME 	 [all_outputs]
    136. set_load 		  [expr {$MAX_LOAD * 3}] 			 [all_outputs]
    137. set_isolate_ports -type buffer 					 	 [all_outputs]
    138.  
    139.  
    140. # |===========================================================
    141. # |STEP 8: set max delay for comb logic 
    142. # |===========================================================
    143. # set_input_delay  [expr $CLK_PERIOD * 0.1] -clock $CLK_NAME -add_delay [get_ports I_1]
    144. # set_output_delay [expr $CLK_PERIOD * 0.1] -clock $CLK_NAME -add_delay [get_ports O_1]
    145.  
    146.  
    147. # |===========================================================
    148. # |STEP 9: set operating condition & wire load model 
    149. # |===========================================================
    150. set_operating_conditions -max 			$OPERATE_CONDITION \
    151. 						 -max_library 	$LIB_NAME
    152.  
    153. set 					 auto_wire_load_selection false
    154. set_wire_load_mode  	 top
    155. set_wire_load_model		 -name    $WIRE_LOAD_MODEL \
    156. 						 -library $LIB_NAME
    157.  
    158.  
    159. # |===========================================================
    160. # |STEP 10: set area constraint (Let DC try its best) 
    161. # |===========================================================
    162. set_max_area			 1000
    163.  
    164.  
    165. # |===========================================================
    166. # |STEP 11: set DRC constraint 
    167. # |===========================================================
    168. # set MAX_CAPACITANCE [expr {[load_of $LIB_NAME/NAND4X2/Y] * 5}]
    169. # set_max_capacitance $MAX_CAPACITANCE $ALL_INPUT_EXCEPT_CLK
    170.  
    171.  
    172. # |===========================================================
    173. # |STEP 12: set group path
    174. # |Avoid getting stack on one path
    175. # |===========================================================
    176. # group_path -name $CLK_NAME -weight 5 				\
    177. # 						   -critical_range  [expr {$CLK_PERIOD * 0.1}] 
    178.  
    179. # group_path -name INPUTS    -from [all_inputs] 		\
    180. # 					 	   -critical_range  [expr {$CLK_PERIOD * 0.1}] 
    181.  
    182. # group_path -name OUTPUTS   -to [all_outputs] 		\
    183. # 						   -critical_range  [expr {$CLK_PERIOD * 0.1}] 
    184.  
    185. # group_path -name COMBS     -from [all_inputs] 		\
    186. # 						   -to [all_outputs] 		\
    187. # 						   -critical_range  [expr {$CLK_PERIOD * 0.1}] 	
    188. # report_path_group
    189.  
    190.  
    191. # |===========================================================
    192. # |STEP 13: Elimate the multiple-port inter-connect &
    193. # |			define name style
    194. # |===========================================================
    195. # set_app_var 						verilogout_no_tri 					true
    196. # set_app_var						verilogout_show_unconnected_pins 	true
    197. # set_app_var						bus_naming_style					{%s[%d]}
    198. # simplify_constants 				-boundary_optimization
    199. # set_boundary_optimization 		[current_design] 					true
    200. # set_fix_multiple_port_nets 		-all 								-buffer_constants
    201.  
    202.  
    203. # |===========================================================
    204. # |STEP 14: timing exception define
    205. # |===========================================================
    206. # set_false_path -from [get_clocks I_CLK_100M] -to [get_clocks I_CLK_100M]
    207. # set ALL_CLKS [all_clocks]
    208. # foreach_in_collection CUR_CLK $ALL_CLKS 
    209. # {
    210. # 	set OTHER_CLKS [remove_from_collection [all_clocks] $CUR_CLK]
    211. # 	set_false_path -from $CUR_CLK $OTHER_CLKS
    212. # }
    213.  
    214. # set_false_path -from [get_clocks I_CLK_100M] -to [get_clocks I_CLK_100M]
    215. # set_false_path -from [get_clocks I_CLK_100M] -to [get_clocks I_CLK_100M]
    216.  
    217. # set_disable_timing TOP/U1 -from a -to y
    218. # set_case_analysis 0 [get_ports sel_i]
    219.  
    220. # set_multicycle_path -setup 6 -from FFA/CP -through ADD/out -to FFB/D
    221. # set_multicycle_path -hold 5 -from FFA/CP -through ADD/out -to FFB/D
    222. # set_multicycle_path -setup 2 -to FFB/D
    223. # set_multicycle_path -hold 1 -to FFB/D
    224.  
    225.  
    226.  
    227. # |===========================================================
    228. # |STEP 15: compile flow
    229. # |===========================================================
    230. # ungroup -flatten -all
    231.  
    232. # 1st-pass compile
    233. # compile -map_effort high -area_effort high
    234. # compile -map_effort high -area_effort high -boundary_optimization
    235. compile 
    236.  
    237. # simplify_constants -boundary_optimization
    238. # set_fix_multiple_port_nets -all -buffer_constants
    239.  
    240. # compile -map_effort high -area_effort high -incremental_mapping -scan
    241.  
    242. # 2nd-pass compile
    243. # compile -map_effort high -area_effort high -incremental_mapping -boundary_optimization
    244. # compile_ultra -incr
    245.  
    246.  
    247. # |===========================================================
    248. # |STEP 16: write post-process files
    249. # |===========================================================
    250. # change_names -rules verilog -hierarchy
    251. # remove-unconnected_ports [get_cells -hier *] -blast_buses
    252. # Write the mapped files
    253. write -f ddc -hierarchy -output $MAPPED_PATH/${TOP_MODULE}.ddc
    254. # write 	-f verilog 	-hierarchy -output 	$MAPPED_PATH/${TOP_MODULE}.v
    255. # write_sdc -version 	1.7 				$MAPPED_PATH/${TOP_MODULE}.sdc
    256. # write_sdf -version 	2.1 				$MAPPED_PATH/${TOP_MODULE}.sdf
    257.  
    258. # |===========================================================
    259. # |STEP 17: generate report files
    260. # |===========================================================

    在完成编译之后可以用本篇的PPT里面介绍的 时序报告指令进行时序分析。此处不再赘述。

    TCL编程练习

    1.  
    2. # |================================= Tcl coding practice ===========================
    3. # |Coded by:Xu Y. B.
    4. # |Date:2022-11-25
    5. # |Description:basic Tcl syntax 
    6. # |=================================================================================
    7.  
    8. # ******** example :define your variable  
    9. set FILE_NAME Sample_Test
    10. set VAR_1	  0
    11.  
    12. # ******** example :if-else 
    13. if {$VAR_1 == 0} {
    14. 	echo "Your variable VAR_1 is 0"
    15. }  else  {
    16. 	echo "Your variable VAR_1 is not 0"
    17. }
    18.  
    19. # ******** example :switch
    20. switch -regexp   $FILE_NAME {
    21. 	"Sample_Test" {
    22. 		echo "The File is Right"	
    23. 	}
    24. 	"Test" {
    25. 		echo "The File is others"
    26. 	}
    27. 	default {
    28. 		echo "The File is nothing !"
    29. 	}
    30. }
    31.  
    32. # ********* example :while
    33. set i 1
    34. while {$i <= 10} {
    35. 	echo "i = $i";
    36. 	incr i 1;	
    37. }
    38.  
    39. # ********* example :for
    40. for {set i_a 0} {$i_a <= 20} {incr i_a 2} {					
    41. 	if {$i_a == 4 || $i_a == 18} {					
    42. 		continue;						
    43. 		# break;						
    44. 	}					
    45. 	echo "i_a = $i_a";					
    46. }					
    47.  
    48. # ********* example :foreach
    49. # example 1
    50. set MY_LIST [list "Xu Y. B." "is" 23 "years" "old"]
    51.  
    52. foreach MY_LIST $MY_LIST {
    53. 	switch -regexp $MY_LIST {
    54. 		"Xu Y. B." {
    55. 			echo "$MY_LIST is a name"
    56. 		}
    57. 		23 {
    58. 			echo "$MY_LIST is a number"
    59. 		}
    60. 		default {
    61. 			echo "$MY_LIST"
    62. 		}
    63. 	}
    64. }
    65.  
    66. # example 2
    67. set log_file_cnt 0
    68. set v_file_cnt   0
    69. set tcl_file_cnt 0
    70.  
    71. set my_file_list [glob *.log *.v *.tcl]
    72.  
    73. foreach f_name $my_file_list {
    74. 	set f_ext [file extension $f_name]
    75. 	switch  $f_ext {
    76. 		".log" {
    77. 			incr log_file_cnt
    78. 		}
    79. 		".v" {
    80. 			incr v_file_cnt
    81. 		}
    82. 		".tcl" {
    83. 			incr tcl_file_cnt
    84. 		}
    85. 	}
    86. }
    87.  
    88. echo "The current folder contains totally .log file number is $log_file_cnt";
    89. echo "The current folder contains totally .v file number is $v_file_cnt"
    90. echo "The current folder contains totally .tcl file number is $tcl_file_cnt"
    91.  
    92. # ********** example :Write something to a file
    93. set   TEXT_W "Xu Y. B. is my name"
    94. set   FILE_ID_W [open TEST.txt w+]
    95. puts  $FILE_ID_W $TEXT_W
    96. flush $FILE_ID_W
    97. close $FILE_ID_W
    98.  
    99.  
    100. # ********** example :Read something from a file
    101. set TEXT_R ""
    102. set FILE_ID_R [open TEST.txt r]
    103. gets $FILE_ID_R TEXT_R
    104. echo "\" $TEXT_R \"is read from file id $FILE_ID_R"
    105.  
    106. close $FILE_ID_R
    107.  
    108. # ********** example :proc
    109. # example 1:
    110. set NAME "Xu Y. B."
    111.  
    112. proc my_print_var {var_name} \
    113. {	
    114. 	global NAME
    115. 	echo "var_name is \" $var_name \""
    116. 	echo "var_name is \" $NAME \""
    117. }
    118.  
    119. my_print_var NAME
    120.  
    121.  
    122. # example 2:
    123. proc min {a b c d} \
    124. {
    125. 	if {$a >= $b} {
    126. 		set y $b;
    127. 	} else {
    128. 		set y $a;
    129. 	}
    130.  
    131. 	if {$c >= $d} {
    132. 		set z $d;
    133. 	} else {
    134. 		set z $c;
    135. 	}
    136.  
    137. 	if {$y >= $z} {
    138. 		set w $z;
    139. 	} else {
    140. 		set w $y
    141. 	}
    142. 	return $w;
    143. }
    144.  
    145. # min 11 21 3 4
    146.  
    147.  
    148. # example 3 :
    149. proc sum {args} \
    150. {
    151. 	set num_list $args
    152. 	set sum 0
    153. 	foreach num $num_list {
    154. 		set sum [expr ($sum + $num)]
    155. 	}
    156. 	return $sum
    157. }
    158.  
    159. # sum 1 2 3 4
    160.  
    161. # example 4 :
    162. # array set PORTS [list I_CLK 3 I_RSTN 4 I_DATA 5 O_DATA 6]
    163. set PORTS {I_CLK 12 I_RSTN 4 I_DATA 5 O_DATA 6}
    164.  
    165. proc inc_port {port_num_list} \
    166. {
    167. 	array set PORTS_1 $port_num_list
    168. 	set port_list [array names PORTS_1]
    169. 	foreach port $port_list {
    170. 		incr PORTS_1($port) 20
    171. 	}
    172. 	return [array get PORTS_1]
    173. }
    174.  
    175.  
    176. # inc_port  $PORTS
    177.  
    178. # example 5 :
    179. # create a link to the variable outside
    180. set NUMBER 0					
    181. proc incr_ten {num} {					
    182. 	upvar $num local_var					
    183. 	incr local_var 10					
    184. }					
    185. 					
    186. incr_ten $NUMBER					
    187.

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  • 原文地址：https://blog.csdn.net/qq_43045275/article/details/128007054