异步FIFO
`timescale 1ns/1ns
module dual_port_RAM #(parameter DEPTH = 16,
parameter WIDTH = 8)(
input wclk
,input wenc
,input [$clog2(DEPTH)-1:0] waddr
,input [WIDTH-1:0] wdata
,input rclk
,input renc
,input [$clog2(DEPTH)-1:0] raddr
,output reg [WIDTH-1:0] rdata
);
reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];
always @(posedge wclk) begin
if(wenc)
RAM_MEM[waddr] <= wdata;
end
always @(posedge rclk) begin
if(renc)
rdata <= RAM_MEM[raddr];
end
endmodule
module asyn_fifo#(
parameter WIDTH = 8,
parameter DEPTH = 16
)(
input wclk ,
input rclk ,
input wrstn ,
input rrstn ,
input winc ,
input rinc ,
input [WIDTH-1:0] wdata ,
output wire wfull ,
output wire rempty ,
output wire [WIDTH-1:0] rdata
);
localparam ADDR_WIDTH = $clog2(DEPTH);
dual_port_RAM #(
.WIDTH(WIDTH),
.DEPTH(DEPTH)
)
u_dual_port_RAM(
.wclk (wclk) ,
.wenc (winc&&!wfull) ,
.waddr (wr_addr_bin[ADDR_WIDTH-1:0]) ,
.wdata (wdata) ,
.rclk (rclk) ,
.renc (rinc&&!rempty) ,
.raddr (rd_addr_bin[ADDR_WIDTH-1:0]) ,
.rdata (rdata)
);
reg [ADDR_WIDTH:0] wr_addr_bin;
wire [ADDR_WIDTH:0] wr_addr_gray;
reg [ADDR_WIDTH:0] wr_addr_gray_d;
reg [ADDR_WIDTH:0] wr2rd_addr_gray_d1;
reg [ADDR_WIDTH:0] wr2rd_addr_gray_d2;
reg [ADDR_WIDTH:0] rd_addr_bin;
wire [ADDR_WIDTH:0] rd_addr_gray;
reg [ADDR_WIDTH:0] rd_addr_gray_d;
reg [ADDR_WIDTH:0] rd2wr_addr_gray_d1;
reg [ADDR_WIDTH:0] rd2wr_addr_gray_d2;
always @(posedge wclk or negedge wrstn) begin
if(!wrstn)
wr_addr_bin <= 'b0;
else if(winc&&!wfull)
wr_addr_bin <= wr_addr_bin + 1'b1;
else
wr_addr_bin <= wr_addr_bin;
end
always @(posedge rclk or negedge rrstn) begin
if(!rrstn)
rd_addr_bin <= 'b0;
else if(rinc&&!rempty)
rd_addr_bin <= rd_addr_bin + 1'b1;
else
rd_addr_bin <= rd_addr_bin;
end
assign wr_addr_gray = wr_addr_bin^(wr_addr_bin>>1'b1);
assign rd_addr_gray = rd_addr_bin^(rd_addr_bin>>1'b1);
always @(posedge wclk or negedge wrstn) begin
if(!wrstn)
wr_addr_gray_d <= 'b0;
else
wr_addr_gray_d <= wr_addr_gray;
end
always @(posedge rclk or negedge rrstn) begin
if(!rrstn)
rd_addr_gray_d <= 'b0;
else
rd_addr_gray_d <= rd_addr_gray;
end
always @(posedge wclk or negedge wrstn) begin
if(!wrstn) begin
rd2wr_addr_gray_d1 <= 'b0;
rd2wr_addr_gray_d2 <= 'b0;
end
else begin
rd2wr_addr_gray_d1 <= rd_addr_gray_d;
rd2wr_addr_gray_d2 <= rd2wr_addr_gray_d1;
end
end
always @(posedge rclk or negedge rrstn) begin
if(!rrstn) begin
wr2rd_addr_gray_d1 <= 'b0;
wr2rd_addr_gray_d2 <= 'b0;
end
else begin
wr2rd_addr_gray_d1 <= wr_addr_gray_d;
wr2rd_addr_gray_d2 <= wr2rd_addr_gray_d1;
end
end
assign wfull = (wr_addr_gray_d == {~rd2wr_addr_gray_d2[ADDR_WIDTH:ADDR_WIDTH-1], rd2wr_addr_gray_d2[ADDR_WIDTH-2:0]});
assign rempty = (rd_addr_gray_d == wr2rd_addr_gray_d2);
endmodule
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