Using power MOSFETs in parallel

REF

1.  Using power MOSFETs in parallel

https://assets.nexperia.com/documents/application-note/AN11599.pdf

 

2. Parallel Connection of IGBT and MOSFET Power Modules.

https://www.microsemi.com/document-portal/doc_download/14723-parallel-connection-of-igbt-mosfet-power-modules

3. MOSFET Paralleling (Parasitic Oscillation between Parallel Power MOSFETs)

https://www.mouser.com/pdfDocs/MOSFET_Paralleling.pdf

4. Driving Parallel MOSFETs Using the DRV3255-Q1

https://www.ti.com/lit/an/slvaf39a/slvaf39a.pdf

5. MOSFET Parallel Operation (TK62N60X) Reference Guide

https://toshiba-semicon-storage.com/content/dam/toshiba-ss-v3/master/en/semiconductor/design-development/referencedesign/RD010-RGUIDE-02_E.pdf

6. https://www.ti.com/lit/an/slva959b/slva959b.pdf?ts=1664203499098Best Practices for Board Layout of Motor Drivers

https://www.ti.com/lit/an/slva959b/slva959b.pdf?ts=1664203499098

Paralle MOSFET using for Power Supply Switch, and  Motor Drivering Swicth. Static operation and Dynamic operation.

Note

1. Using the same Production lot.

2. The Parallel MOSFET should be matched before using in a group. 

Schematic Diagram

Note that because the limiting resistor is now being placed in parallel for each MOSFET, the individual resistance must be increased to maintain the same equivalent resistance. For example, if an individual 10-Ω resistor was used on a single gate, each gate in a dual MOSFET configuration would need a 20-Ω resistor so that the equivalent resistance is still 20 || 20 = 10.

 

 

        

PCB Layout 

Theory

Increasing the current-conducting capability of a halfbridge circuit benefits from lower RDS(on) and therefore reduced power loss to heat. Designers often use multiple FETs in parallel since FETs placed in parallel will result in an effective reduction in RDS(on) that can still be driven by one gate output. From a theoretical standpoint these multiple FETs can be treated as a single component, as Figure 1 shows.

 

Layout Gate Considerations 

 The following guidelines are helpful for the best performance of the MOSFET gates:

• To switch the MOSFETs as simultaneously as possible and minimize power losses, try to place MOSFETs in close proximity to each other.

• Keep the gate traces unified until close to the MOSFETs. This will minimize the chance of external signal coupling affecting the MOSFETs differently

• Keep the length of the individual gate traces reasonably close, although precision length matching usually is not necessary.

• Placement of the individual gate resistors is not critical, but it is recommended to place them close to the MOSFETs, when possible, to limit the chance for signals to couple into or out of the MOSFET gates.

 

 Layout Drain and Source Considerations

The following guidelines are helpful for best performance of the MOSFET Drain and Source connections:

• To switch the MOSFETs as simultaneously as possible and minimize power losses, try to keep MOSFET drain and source connections as similar as possible.

• Ensure that the source and drain connections for both MOSFETs have strong connections (polygon copper pours are highly recommended instead of traces) so that current flow is relatively even. If current flow through one of the MOSFETs is limited by the source or drain connection, it will cause the other MOSFET to take a disproportionate amount of the current, potentially causing thermal issues.

• Thermal relief of the pads is not advised as this reduces current carrying capability and increases thermal resistance which will reduce MOSFET heat sinking to the PCB.

 

Using power MOSFETs in parallel

2. Static (DC) operation

This situation is the simplest condition where current flows through a group of paralleled MOSFETs that are fully enhanced (switched ON). A proportion of the total current flows through each MOSFET in the group. At the initial point of turn on, the die temperatures of all the MOSFETs in the group are the same. The drain current ID flowing in each MOSFET is inversely proportional to its RDS(on) (the drain-source voltage VDS across all the MOSFETs is the same).

The MOSFET with the lowest RDS(on) takes the highest proportion of the current and dissipates the most power (power dissipation P = VDS x ID).

All the MOSFETs heat up, but the MOSFET with the lowest RDS(on) heats up most (assuming the Rth(j-a) of all the MOSFETs is the same)

MOSFET RDS(on) has a positive temperature coefficient. RDS(on) increases as Tj increases. The die temperatures and RDS(on) values of all MOSFETs in the group rise, but the die temperature of the lowest RDS(on) MOSFET increases disproportionately. The effect of this behavior is to redistribute the current towards the other (higher RDS(on)) MOSFETs in the group.

Stable thermal equilibrium is reached after a period of operation. The lowest RDS(on) MOSFET is the hottest, but carries a lower proportion of the current than it did initially.

The Positive Temperature Coefficient (PTC) of RDS(on) is a stabilizing influence that promotes power sharing between the MOSFETs in the group. However, as stated earlier the most important criterion is that the maximum junction temperature of any MOSFET in the group must not exceed 175 ℃.

The cooling of each MOSFET in the group depends on its thermal resistance from junction to ambient. Die temperature influences the heat flow from adjacent MOSFETs. Rather than considering the thermal resistance paths between the MOSFET dies, the main influence is the temperature of the common heatsink. All the MOSFET mounting bases are bonded electrically and thermally to this heatsink.

The lowest RDS(on) MOSFET could be located anywhere in the group. The thermal resistance from mounting base to ambient of all the MOSFETs in the group should be as similar as possible and as low as possible. Cooling is optimized and independent of location.

This thermal resistance solely depends on the thermal characteristics and design of the assembly [Printed-Circuit Board (PCB) or heatsink] to which the MOSFET is thermally bonded.

Sometimes a value for Rth(j-a) is given in data sheets but this parameter is of very limited value. It cannot be treated as a well-defined parameter because it also depends on other external factors such as PCB construction, PCB orientation and air flow. The only guaranteed thermal parameter is the thermal resistance from the MOSFET junction to mounting base Rth(j-mb).

2.1 Worked examples for static operation

        

A typical group of MOSFETs has a range of RDS(on) values. The distribution has a peak at around the typical data sheet RDS(on) value; none should have an RDS(on) higher than the data sheet maximum. The RDS(on) of about half of the samples is less than the typical value. 

 The RDS(on) value range means that a group of typical MOSFETs is very unlikely to share power equally when they are operated in parallel.

The worst case would be when one of the MOSFETs has the minimum RDS(on) and all the others have the maximum RDS(on).

Modeling of the electro-thermal system is complex because its electrical and thermal characteristics are mutually dependent. However, an electro-thermally convergent Excel model can be used to estimate the performance characteristics of a paralleled group. As an example, in a worst case situation three BUK764R0-40E MOSFETs are connected in parallel; two have maximum RDS(on) of 4 mΩ. The other has a lower than typical RDS(on) of 2.6 mΩ.

The MOSFET with the lowest RDS(on) value takes the highest proportion of the current. It therefore has the highest power dissipation.

The target is to keep the junction temperature of the hottest MOSFET below 175 ℃ C under worst case operating conditions. These estimations are simplified illustrations. The thermal representation of the MOSFET group is less complex than a real application. In a real application, there are other factors such as neighboring components and orientation that would influence cooling. However, they show the approximate behavior of the group with two different Rth(j-a) values.

The first scenario shows the system with the thermal resistance from junction to ambient for each MOSFET (Rth(j-a) = 20 K/W; Tamb = 125 ℃).

 

 

 Total initial power P(M1 + M2 + M3) = 10.70 W

Total final power P(M1 + M2 + M3) = 5.82 W

The second scenario relates to the same electrical system, but with ideal thermal characteristics. The thermal resistance Rth(j-a) of each MOSFET is 0.82 K/W. This situation corresponds to the ideal but unrealistic situation where each MOSFET is perfectly thermally bonded to an infinite heatsink (a heatsink with zero thermal resistance).

 Total initial power P(M1 + M2 + M3) = 267.60 W

Total final power P(M1 + M2 + M3) = 145.39 W

Note: This scenario is ideal and unrealistic. It is included to illustrate the benefit of reducing Rth(j-a) to maximize the usage of the MOSFET capabilities

 

In practice, Rth(j-a) is always greater than Rth(j-mb). The thermal bonding between the MOSFET mounting base and the heatsink is never perfect and an infinite heatsink does not exist in the real world.

In this case, the drain current (ID) of the MOSFETs becomes the limiting factor (the data sheet maximum ID is 75 A).

To optimize MOSFET utilization, the MOSFETs must be able to dissipate as much power as possible. At the same time, the junction temperature of the hottest MOSFET must remain below the maximum safe temperature of 175 ℃.

The following conclusions can be drawn from Table 2 and Table 3:

1. It is beneficial to reduce Rth(j-a) as much as possible to optimize the MOSFET die cooling.

2. It is beneficial to reduce the maximum ambient temperature to increase the available thermal 'headroom'.

3. As a result of Table 2 and Table 3, it is clear that junction temperature difference between the MOSFETs depends only on their RDS(on) values (assuming the Rth(j-a) for each MOSFET is the same).

4. When the paralleled (fully enhanced) MOSFETs heat up during use, their power distribution changes such that the cooler MOSFETs take a greater proportion of the power. This effect is due to the PTC of RDS(on) and it acts to promote thermal stability

3. MOSFET mounting for good thermal performance and power sharing

To get the most from the MOSFET group, the individual MOSFET should be mounted in a way that causes their mounting base temperatures to be as similar as possible and also as low as possible.

To realize this goal, the thermal resistance between each MOSFET (mounting base) and the mounting bases of all the other MOSFETs in the group should be matched and minimized. They should be mounted symmetrically and as close together as possible on a thermally conductive surface.

Heat flow can be considered to be analogous to electric current flow; so the thermal bonding points of the MOSFETs (usually the drain tabs) should be on a thermal ‘ring main’. The low thermal resistance path allows heat to flow easily between the MOSFETs. When heat flows easily between all the MOSFETs in the group, their mounting base temperatures track together closely.

Note: This arrangement does not promote equal current sharing, but promotes better die temperature matching. The temperatures of all the MOSFETs in the group can rise more before the temperature of the hottest MOSFET reaches 175 C. Hence the power dissipation capability of the group is maximized.

There are practical limits to the physical extent of the thermal ring main; ideally each MOSFET should be next to all its neighbors. This condition limits the group to two or three MOSFETs.

 

 A good way to parallel a pair of MOSFETs is to locate them on opposite faces of a PCB forming a PCB ‘sandwich’ as in Figure 4a. Thermal vias between the copper ‘land’ areas on the PCB reduce the electrical and thermal resistances between their mounting bases.

To parallel a pair of MOSFETs on the same face of a PCB, they can be mounted next to each other as in Figure 4b.

A good way to parallel three MOSFETs is in a ring as in Figure 4c. This arrangement allows all the MOSFET sources in the group to be connected to a ‘star’ point. The electrical and thermal paths between the MOSFET drains match due to their symmetrical connections to the drain loop

Minimizing and matching the electrical impedances in the source paths is more important than matching the electrical impedance in the drain paths. This difference is because their gate drives are related to the sources. Good impedance matching in both drain and source is more important in high frequency switching circuits.

If similar electrical and thermal matching can be achieved, larger paralleled groups could be considered. Groups of more than four or five become unwieldy so grouped sub groups should be used.

 In this group of 9 (3 groups of 3), there is a natural drain star point at the center of the group. There are separate source star points at the centers of each sub group. The source star points can be connected on a layer of a multi-layer PCB.

There is a compromise between optimizing layout for power sharing and maximizing PCB usage.

Electrically and thermally optimized layouts always use more PCB area than the minimum possible, but utilization of MOSFET capability should be better. Areas of PCB that are unoccupied by MOSFETs or gate drive components are useful for thermal interfaces with heat sink or cooling air.

4. Power sharing in dynamic operation [pulse and Pulse Width Modulation (PWM) circuits]

Many MOSFET circuits are designed to operate in systems where they are switched repetitively (such as DC-to-DC converters). Paralleled MOSFETs can be used as the switching elements in the system, but in addition to the guidelines set out for optimal steady state power sharing. Some additional points must be considered so that the MOSFETs share current during the switching transitions.
Good circuit and layout design is important. It influences the proportion of current carried by each MOSFET in the group during and after the switching event.

 Figure 7a and Figure 7b show how the current distribution in three paralleled MOSFETs initially depends on the source inductances in the MOSFET current paths, namely L1, L2 and L3. As time progresses the resistances in the MOSFET current paths, namely RDS(on) + R1, RDS(on) + R2 and RDS(on) + R3 determine the current distribution.

The same principles hold about impedance matching of the current paths to the MOSFETs in the group. In this case, it is more important for the rates of change of current in the MOSFETs to match. The source inductances are the key impedance as they affect the gate-source voltages (gate drives) of the MOSFETs in the group.

This effect dominates more in high frequency and short duty cycle applications (e.g. switched-mode power supplies). It may be insignificant in lower frequency applications such as motor drives.

5. Partially enhanced (linear mode) power sharing

If a group of MOSFETs must operate in linear (partially enhanced) mode, great caution is needed. MOSFETs simply paralleled together as they are for fully enhanced conduction are very unlikely to share power or current well.

This behavior is due to the Negative Temperature Coefficient (NTC) of gate threshold voltage VGS(th). As the group of MOSFETs starts to enhance, the MOSFET with the lowest VGS(th) starts to conduct channel current first. It dissipates more power than the others and heat up more. Its VGS(th) decreases even further which causes it to enhance further.

This unbalanced heating causes the hottest MOSFETs to take a greater proportion of the power (and get even hotter). This process is unsustainable and can result in MOSFET failure if the power is not limited. Great care is needed when designing paralleled power MOSFET circuits that operate in the partially enhanced (linear mode) condition.

If all the MOSFETs in the group operate within their Safe Operating Area (SOA), they work reliably. The SOA must be adjusted for the worst case mounting base temperature that occurs in the application. Remember that the data sheet SOA graph applies only if the MOSFET mounting base temperature is 25 C or less.

Adding external source resistors (R1 to R4 in the schematic; see Figure 8) provides the negative feedback needed for stable operation. The gate-source voltage applied to

VGS(M1) = VG - ID(M1) x R1.

If the MOSFETs must also operate in fully enhanced mode (e.g. in ‘Hot Swap’ or ‘Soft Start’ applications), the inclusion of these resistors is an efficiency disadvantage.

As the MOSFET channel current increases, its gate drive voltage reduces.

As the MOSFETs are operating in partial enhancement (where MOSFET RDS(on) is not important), there is no adverse effect caused by including these resistors. If the MOSFETs must operate in both modes (as with active clamping after fully enhanced conduction), the inclusion of source resistors does have a negative impact.

 

6. Gate drive considerations

It is preferable to fit low value gate resistors between the gate driver and the gate of each MOSFET in the group. Their main function is to decouple the MOSFET gates from each other so they all receive similar gate drive signals.

Without these resistors, at turn on the Miller plateau of the MOSFET with the lowest threshold voltage would act to clamp the gate-source voltages of the other MOSFETs in the group. This clamping effect tends to inhibit and delay the turning on of the other MOSFETs in the group. At turn off a similar process occurs.

Without these resistors, the MOSFET with the lowest threshold voltage would switch on first and switch off last. The consequences of this effect may be insignificant in low frequency high duty cycle applications. In higher frequency PWM applications, it could cause a significant power imbalance between the MOSFETs. Positive feedback also occurs in this case which increases the imbalance and could ultimately cause MOSFET failure.

Gate resistors also help to damp out oscillatory transients on VGS. They also swamp any effects caused by variations in the internal gate resistance RG(int) of the MOSFETs.

6.1 Should individual gate drivers be used for each MOSFET in the group?

Using individual gate drivers for each MOSFET in the group is usually unnecessary. They may be necessary in applications where fast switching of a large group of large die MOSFETs is needed. Here the MOSFETs should be arranged in smaller sub groups, each sub group driven by an individual gate driver. Care should be taken to balance the circuit so the propagation delays of all the gate drivers are similar. This matching ensures that the switching of all the MOSFETs in the group is synchronized. Usually it is sufficient to drive the gate of each MOSFET in the group from the same gate driver. However, it is important to have a gate resistor between the gate driver output and the gate of each MOSFET as mentioned earlier.

 7. MOSFET packaging considerations for paralleled groups

Conventionally packaged surface-mounted MOSFETs (DPAK and D2PAK) are the most widely available types so they are considered first for paralleled groups. However, KGD and LFPAK (power SO8) MOSFETs could offer better solutions.

7.1 Bare die (KGD) MOSFETs

These MOSFETs offer the densest and most flexible options for paralleled groups; they are designed to suit a specific application. The die aspect ratio and gate pad location can be designed specifically to suit the application. More source wire bonds can be fitted to the die than can be fitted in a conventionally packaged MOSFET, so overall RDS(on) can be reduced. Maximum drain current can be increased to achieve better performance from a paralleled group of MOSFETs. Special manufacturing facilities are required for KGD assembly.

7.2 LFPAK MOSFETs

The power SO8 (LFPAK) MOSFETs offer the opportunity to manufacture the paralleled MOSFET circuit conventionally. Higher component density and power capability are possible (approaching that of KGDs). The connections to the source and gate are made using copper clips which give better electrical and thermal performance than aluminum wire bonds in conventional packages.

8. Inductive energy dissipation in paralleled MOSFETs

8.1 Avalanching - low side MOSFET group driving a high side inductive load

If the group of paralleled MOSFETs is driving an inductive load, energy stored in this load must be safely dissipated when the current is switched off. A good way to manage this energy is to connect a ‘freewheel diode’ across the load; see Figure 9. Current flowing in the MOSFET channel diverts into the diode when the MOSFETs switch off and the energy is dissipated in the circuit resistances. However, it is not always possible and energy must then be dissipated safely in the MOSFETs.

If the battery polarity (Vsup) is reversed, the low impedance path through the freewheel diode and the body diode can carry large damaging currents. Freewheel diodes are often not used for this reason.

When the group of MOSFETs is switched off, the back e.m.f. from the inductive load may be high enough to cause the drain-source voltage across the group of MOSFETs to exceed the drain-source breakdown voltage V(BR)DSS of one of the MOSFETs. It likely that MOSFETs in the group have a range of V(BR)DSS values (even though they are the same type). The current then flows through the body diode of the MOSFET with the lowest V(BR)DSS in reverse (avalanche) conduction. This condition causes high-power dissipation and temperature rise in the MOSFET die (P = ID x V(BR)DSS). If the maximum 175 ℃ junction temperature is exceeded, the thermal stress on the die could degrade or destroy the MOSFET.

In the worst case, all the current which was flowing through the group of MOSFETs could be diverted into the body diode of one MOSFET in the group. If this scenario is possible, it is vital that a single MOSFET in the group can safely handle the total avalanche current under worst case thermal conditions. V(BR)DSS has a positive temperature coefficient which tends to redistribute the current towards other MOSFETs with higher V(BR)DSS values.

 8.2 Active clamping - high side MOSFET group driving a low side inductive load

This configuration (see Figure 10) is often used in automotive applications. This topology is useful because the vehicle chassis can be used as the negative supply return path to the battery.

In this circuit, the difference between the threshold voltages rather than V(BR)DSS spread determines where the load current flows. The MOSFET with the lowest threshold voltage conducts the greatest proportion of the current. The drain-source voltage across the MOSFET group is Vsup + VGS and the power dissipation of the group is (Vsup + VGS) x ID. As with the avalanche case, all the current (and hence all the power dissipation) could be diverted into a single MOSFET in the group.

This situation is worse than the avalanche case because MOSFET threshold voltage has a negative temperature coefficient. This characteristic tends to direct the current flow initially to the hottest MOSFET. This MOSFET then gets even hotter so that it retains the current.

9. Summary

1. It is better to use a single large MOSFET rather than a group of smaller MOSFETs.

2. The power capability of a group of n MOSFETs never achieves n times the power capability of a single MOSFET.

3. If it is necessary to use paralleled MOSFETs, use the lowest number possible as the basic group size (3 maximum).

4. If a larger number is needed, use a group of basic groups i.e. 4 = 2 groups of 2; 6 = 2 groups of 3.

5. The circuit layout is a very important factor determining how well a group of paralleled MOSFETs share power dissipation, particularly in higher frequency repetitive switching circuits.

6. Consider LFPAKs (for repetitive switching applications) because of their small size, good thermal performance and low package impedances.

7. Special care is needed when designing groups of MOSFETs that could operate in avalanche or active clamping mode.

MOSFET Paralleling (Parasitic Oscillation between Parallel Power MOSFETs)

This document explains structures and characteristics of power MOSFETs.

4.2.2. Preventing oscillation

 

MOSFET Parallel Operation (TK62N60X) Reference Guide

1. Introduction

For power supply and other applications that MOSFETs are used as switching devices, in order to develop a new design with a higher output power based on an existing design, it is necessary to:

1. design a new topology or circuit configuration, or

2. replace MOSFETs with higher current rating (i.e., low on-resistance) without modification of the topology or circuit configuration. 

The latter approach helps save a lot of development time. However, there is a limitation in increasing the current rating of a MOSFET without changing the package. To increase the output power of a design, it might be necessary to use MOSFETs in larger packages or use multiple MOSFETs in parallel. Paralleling MOSFETs has several advantages over replacing existing MOSFETs with those in larger packages. For example, since MOSFETs are common heat sources, paralleling MOSFETs makes it possible to spread heat sources apart from one another. In addition, using the same MOSFETs as in an existing system means that the same heat spreaders in the existing systems can be used.

2. Verification of MOSFET operation by simulation

2.1. Simulation model

This section describes the simulation model of the TK62N60X used for verification. The PSpice model of the TK62N60X available on Toshiba’s website characterizes only the chip design. In order to simulate the operation of the TK62N60X including the effect of its package, it is necessary to externally add the parasitic inductances of the TO-247 package to the PSpice model.

Figure 2.1.1 illustrates the internal structure of the TO-247 package and its parasitic inductances. The bonding wires between the MOSFET chip and each of the package terminals have inductances, which are labeled lg, ls and ld in Figure 2.1.1.

Figure 2.1.2 shows a simulation model including the internal parasitic inductances of the TO-247 package for TK62N60X.

 

 

 

 Figure 2.3.1 Simulation circuit

 

 

 

Figure 2.5.2 and Figure 2.5.3 show the simulation results. In Figure 2.5.3, Vgs oscillation is observed, and it indicates that an asymmetrical layout causes an oscillation. Figure 2.5.2 also indicates that MOSFET Q3 with larger source trace inductance turns on later than the other MOSFET Q4, and it is observed current concentration on Q4. An asymmetrical layout is undesirable in terms of both oscillation and current imbalance. It is important to create a layout as symmetrical as possible for parallel MOSFETs.

(Note: In actual operation, a MOSFET with larger current concentration dissipates much heat. This causes its on-resistance to increase, limiting a current. As a result, a current flowing to the other MOSFET increases. Therefore, the currents flowing to the parallel MOSFETs become balanced immediately after turn-on. Since this simulation is not considered heat generation, it took a longer for the currents to the parallel MOSFETs to be balanced.) 

 

 

Figure 2.6.2 and Figure 2.6.3 show the simulation results, which is not observed oscillation. Since it is difficult to create a completely symmetrical layout for parallel MOSFETs, appropriate resistors should be added to the gate of each -MOSFETs. A slight difference in the value of gate resistors does not affect the MOSFET operation and it is acceptable to use general resistors with ±10% tolerance for this purpose. Oscillation was not observed, but unbalanced currents is still occurred during a switching transition.

(Note: In actual operation, a MOSFET with larger current concentration dissipates much heat. This causes its on-resistance to increase, limiting a current. As a result, a current flowing to the other MOSFET increases. Therefore, the currents flowing to the parallel MOSFETs become balanced immediately after turn-on. Since this simulation is not considered heat generation, it took a longer for the currents to the parallel MOSFETs to be balanced.) 

 

 3. Conclusion

We verified the operation of parallel MOSFETs using the TK62N60X of the DTMOSIV series.

As a result, we confirmed that it is important to create a board layout as symmetrical as possible for parallel MOSFETs and add gate resistors between driver IC and MOSFET. When their layout is asymmetrical, the parallel MOSFETs do not turn on simultaneously due to a difference in the source trace inductance, causing a current imbalance during a switching transition. It is necessary to select MOSFETs with appropriate current ratings considering this current imbalance and verify their operation using an actual board.

 Parallel Connection of IGBT and MOSFET Power Modules.

2- Gate drive recommendations 2-1 Electrical diagram

The electrical diagram of power modules connected in parallel is shown on fig.3. It is best to use a common gate driver for all paralleled modules because gate signals are synchronized (uniform propagation delay for each gate). Individual gate drivers for each module could cause some variation in turnon and turn off-delay times, causing asymmetric switching behaviour. This increases even more the switching losses and potential risks of module failures. It is however possible to parallel power modules and their associated drivers if the differences in driver delay times are negligible.

It is imperative that parallel modules have the same part number, and it is also highly recommended to use power modules from the same production lot. This ensures that all devices exhibit the least variation in their characteristics.

It is common practice to implement resistors on the driver to control both turn-on and turn-off behaviour of the power devices. These resistors can be distributed among the modules connected in parallel as gate resistors RG and return gate resistors RE as shown in Fig 3. These resistors dampen the parasitic oscillations that might be induced by cross-coupled gate feedback between devices. In addition, each module’s individual gate / source or gate / emitter is driven in differential mode that compensates negative effects of possible differences in transfer characteristics between modules. The RE value should be lower than RG (In practice RE ≈ RG/3).

If the driver offers dual outputs, gate resistors can be doubled into RG(on) and RG(off) resistors to independently control turn-on and turn-off switching speed, as shown in Fig.4. Main common resistors may be placed on the driver if the distributed gate resistors per module are not sufficient to limit voltage overshoot during switching. It is also recommended to place a resistor (RGE equal to 5kΩ to 10kΩ) as well as a bidirectional tranzorb in parallel with gate and emitter of each module. 

 3-3 Paralleling of SP6 full bridge module.

As the size of a module becomes significant, each switch is made of several cells connected in parallel. Each cell may itself incorporate several dice in parallel. The SP6 full bridge configuration provides gate and source terminals on each side of the module as shown on Fig.5.

The control loop and impedance seen by the gate driver is absolutely identical for each group of dice. The same principle can be extended to many modules in parallel. Fig.7 gives an example of an IGBT module layout and shows again the very symmetrical design, making control signal loops very short and identical. 

 4- Mechanical assembly

Impedance between power source and modules must be as low as possible. It is highly recommended to connect VBUS and 0/VBUS of the modules via laminated bus bars offering very good coupling capacitance and minimum parasitic inductance as shown on Fig. 8.

In any case the parasitic inductance cannot be zero, and fast type capacitors such as polypropylene or even better, ceramic type, must be distributed for each module as close as possible to the power terminals.

It is also important to ensure good current sharing on the power output. If it is not possible to make a very symmetrical layout, it may make sense to insert small inductors with higher impedance than the IGBT between each module output and the load to ensure a good dynamic decoupling of each module output (fig. 9). This should not degrade the performance of the circuit given that in most cases, the load is more or less inductive. The series inductors will tend to decrease the dv/dt applied to the load which may be helpful in some applications.

Conclusion

Paralleling of power modules with good current sharing can be achieved by following some important guidelines. The above recommendations apply both to IGBT and MOSFET modules. However, greater care and maximum precautions are necessary as the number of paralleled modules increases, operating frequencies become very high, and power devices to be paralleled exhibit faster and faster switching times.

Bibliography

- H. Suarez, D. Lafore « Comparaison fonctionnelle des topologies permettant l’intégration d’équilibrage actif de courants dans la mise en parallèle d’IGBTs » EPF 2004.

- S. Lefebvre, et Al., « contrôle des gradients de commutation dans des convertisseurs haute fréquence » EPF 92.

- R. Letor, « static ands dynamic behavior of paralleled IGBTs” IEEE transactions on Industry Applications 1992.

- Undeland T, Kleveland F, Langelid J. “Increase of Output Power from IGBTs in High Power High Frequency Resonant Loads Inverters” IEEE IAS Annual Meeting, Roma 2000.