1 基本概念
1.1 基本概念
SerDes：sir-deez，加串 + 解串；SerDes的lock是指CDR时钟的锁定。
The 10b SerDes (PMA) is designed to support multiple protocols.
1.2 SGMII
SGMII的实现方式一般是GMII-to-SGMII wrapper，然后再连接支持8b/10b编解码的SerDes。SGMII包含6根线，分别是TDP/TDN、RDP/RDN、RCLKP/RCLKN，SGMII分为4-pin和6-pin模式；SGMII模式下GMII的控制信号（TX_EN、TX_ER) 被SGMII wrapper中的8-bit K-code代替，然后8-bit K-code再发送给SerDes，SerDes中的PCS将8-bit K-code编码为10-bit数据后通过并串转换发送出去。SGMII模式和SerDes模式的pin脚是一样的，唯一的区别是SGMII支持10/100/1000 Mbps Auto-Negotiation（AN），而SerDes不支持速率自协商，固定为1000 Mbps。
1.3 MAX24287 SerDes
PCS inside SerDes: Another name of PCS inside SerDes is called Ten Bit Interface (TBI).
PHY = 8b/10b PCS + 10b SerDes (P2S + Output Driver, CDR + S2P)
SGMII = GMII-to-SGMII wrapper + 8/10b PCS + 10b SerDes
SGMII = TBI (GMII-to-SGMII wrapper + 8/10b PCS) + 10b SerDes
SerDes mode: AN Enable + Full Duplex + 1000Mbps
1.4 QSGMII
不同于SGMII 1.25GHz线路速率，QSGMII 5GHz线路速率，以字节交织的方式0/1/2/3，并行传输4路SGMII，编码方式还是8b/10b。参考RTL8218D-CG。
2 SerDes showcase
2.1 freecores / sgmii
Refer to github freecores / sgmii
2.2 OpenSerDes
SparcLab / OpenSERDES
https://github.com/SparcLab/OpenSERDES
2.3 TI SerDes
spruid7e.pdf
AM65x/DRA80xM Processors
Texas Instruments Family of Products
Technical Reference Manual
12.2.4 Serializer/Deserializer (SerDes)
SerDes0: 0x0090_0000
SerDes1: 0x0091_0000
Each SerDes has 158 registers.
PRU_ICSSG2 SerDes Bus Width: 10
USB SerDes Bus Width: 16
2.4 CH569 SerDes
Refer to github wch-ch569-serdes
8b10bIBM_Dotted
8b10bIBM_Hex
4-byte SATA SOF + 4-byte HDR + N-byte DATA + 4-byte SATA CRC + 4-byte SATA EOF
HDR[31:28]: PID, from 0 - 15
HDR[27:0]: customer number assigned by SerDes register DATA0
3 Standalone SerDes
Freescale MC92610
STM C65SPACE-HSSL SerDes, HSSL stands for High Speed Serial Link
4 Abbreviations
comma：K码，0xBC，K28.5
Gsps：Giga samples per second
JESD204B：JEDEC Standard No. 204B
LatticeECP: EConomy Plus, integrate Ethernet SerDes
Msps：Mega-Sample per second
SR ADC：Successive Approximation ADC
UI: 1 bit-time, Unit Interval
WCH: WinChipHead