• 按键中断实验

     按键中断实验

    1、按键电路图分析

    按键抬起时，PF9引脚输入高电平，按键按下时，PF9引脚输入低电平。

    2、分析按键中断的数据手册

    2.1 分析2.5.2章节，确定GPIOF,RCC,EXTI,GIC外设分别接到哪个总线上，以及外设寄存器对应的基地址

    2.2 分析RCC章节，使能GPIOF外设控制器的时钟

    2.3 分析GPIO章节，设置GPIO引脚为输入模式

    2.3.1 GPIOx_MODER寄存器

    2.3.2 GPIOx_PUPDR寄存器

    2.4 分析EXTI章节，设置中断信号的检测

    2.4.1 EXTI_FTSR1寄存器

    1. KEY1--》PF9--》EXTI9---》EXTI9对应的输入事件的编号，需要查看数据手册的21.3章节的表118，如下图所示，
    2. 可知EXTI9对应的输入事件的编号位输入事件9号。
    3.  
    4. EXTI_FTSR1[9]写1，使能下降沿触发中断。及当有下降沿时就认为是一个中断信号。

    2.4.2 EXTI_FPR1寄存器

    1. KEY1--》PF9--》EXTI9---》EXTI9对应的输入事件的编号，需要查看数据手册的21.3章节的表118，
    2. 可知EXTI9对应的输入事件的编号位输入事件9号。
    3.  
    4. EXTI_FPR1[9]写1，清除下降沿中断挂起标志位。

    2.4.3 EXTI_EXTICR3寄存器

    1. EXTI中总共有16个EXTI，从EXTI0-EXTI9，EXTI_EXTICR寄存器的每8位管理一个EXTI外设，
    2. 几个寄存器最多管理4个EXTI,因此需要4个寄存器工程管理16个EXTI。
    3.  
    4. KEY1--> PF9 ---> EXTI9 ---》EXTI_EXTICR3[15:8] ---> 写0x5，将PF9连接到EXTI9上

    2.4.4 EXTI_C1IMR1寄存器

    1. KEY1--》PF9--》EXTI9---》EXTI9对应的输入事件的编号，需要查看数据手册的21.3章节的表118，
    2. 可知EXTI9对应的输入事件的编号为输入事件9号。
    3.  
    4. EXTI_C1IMR1[9]写1，不屏蔽中断信号。

    2.5 分析GIC章节，设置全局中断控制器

    GICD_CTLR : GICD层全局使能寄存器

    GICD_ISENABLER ： GICD层中断设置使能寄存器

    GICD_ICPENDR ：GICD层中断清除挂起寄存器

    GICD_IPRIORITYR ： GICD层中断优先级设置寄存器

    GICD_ITARGETSR ： GICD层中断目标分配寄存器

    GICC_CTLR ： GICC层全局使能寄存器

    GICC_PMR ： GICC层优先级屏蔽寄存器

    GICC_IAR ： GICC层中断应答寄存器

    GICC_EOIR ：GICC层中断处理结束寄存器

    2.5.1 中断号的获取

    每个中断外设都有一个唯一的中断号，通过查看芯片手册的21.2章节的表117，如下图所示：

    KEY1 ---》 PF9 ---》 EXTI9 ----》中断号：99

    2.5.2 GIC全局中断控制器的介绍

    2.5.3 GICD介绍

    2.5.4 GICD_CTLR : GICD层全局使能寄存器

    2.5.5 GICD_ISENABLER ： GICD层中断设置使能寄存器

    1. 前提：KEY1 ---》 PF9 ---》 EXTI9 ----》中断号：99
    2.  
    3. GICD_ISENABLER ： GICD层中断设置使能寄存器
    4.  
    5. GICD_ISENABLER寄存器的每1位管理一个中断号，一个寄存器最多管理32个中断号。
    6. GIC控制器支持16个SGIs，16个PPIs, 256个SPIs, GIC控制器总共支持288个中断号，
    7. GICD_ISENABLER寄存器要想管理288个中断号，最少需要9(288/32)个寄存器。
    8.  
    9. 99号中断对应GICD_ISENABLER寄存器的哪一个，哪一位？
    10. 99 / 32 = 3 ...... 3
    11. 商对应着寄存器的编号，余数对应操作寄存器的位。
    12.  
    13. GICD_ISENABLER3[3] 写1， 使能99号中断

    2.5.6 GICD_ICPENDR ：GICD层中断清除挂起寄存器

    1. 前提：KEY1 ---》 PF9 ---》 EXTI9 ----》中断号：99
    2.  
    3. GICD_ICPENDR ：GICD层中断清除挂起寄存器
    4.  
    5. GICD_ICPENDR寄存器的每1位管理一个中断号，一个寄存器最多管理32个中断号。
    6. GIC控制器支持16个SGIs，16个PPIs, 256个SPIs, GIC控制器总共支持288个中断号，
    7. GICD_ICPENDR寄存器要想管理288个中断号，最少需要9(288/32)个寄存器。
    8.  
    9. 99号中断对应GICD_ICPENDR寄存器的哪一个，哪一位？
    10. 99 / 32 = 3 ...... 3
    11. 商对应着寄存器的编号，余数对应操作寄存器的位。
    12.  
    13. GICD_ICPENDR3[3] 
    14. 	写1， 清除99号中断挂起标志位
    15. 	写0，没有影响
    16. 	
    17. 	读0：表示99号中断没有发生
    18. 	读1：表示99号中断发生

    2.5.7 GICD_IPRIORITYR ： GICD层中断优先级设置寄存器

    1. 前提：KEY1 ---》 PF9 ---》 EXTI9 ----》中断号：99
    2.  
    3. GICD_IPRIORITYR  ： GICD层中断优先级设置寄存器
    4.  
    5. GICD_IPRIORITYR寄存器的每8(5位有效位+3位保留位)位管理一个中断号，一个寄存器最多管理4个中断号。
    6. GIC控制器支持16个SGIs，16个PPIs, 256个SPIs, GIC控制器总共支持288个中断号，
    7. GICD_IPRIORITYR寄存器要想管理288个中断号，最少需要72(288/4)个寄存器。
    8.  
    9. 99号中断对应GICD_IPRIORITYR寄存器的哪一个，哪5位？
    10. 99 / 4 = 24 ...... 3
    11. 商对应着寄存器的编号，(余数*8+3) 对应操作寄存器的最低位。
    12.  
    13. GICD_IPRIORITYR24[31:27]  设置中断的优先等级，数越小，优先级越高
    14.

    2.5.8 GICD_ITARGETSR ： GICD层中断目标分配寄存器

    1. 前提：KEY1 ---》 PF9 ---》 EXTI9 ----》中断号：99
    2.  
    3. GICD_ITARGETSR ： GICD层中断目标分配寄存器
    4.  
    5. GICD_ITARGETSR寄存器的每8(6位保留位+2位有效位)位管理一个中断号，一个寄存器最多管理4个中断号。
    6. GIC控制器支持16个SGIs，16个PPIs, 256个SPIs, GIC控制器总共支持288个中断号，
    7. GICD_ITARGETSR寄存器要想管理288个中断号，最少需要72(288/4)个寄存器。
    8.  
    9. 99号中断对应GICD_ITARGETSR寄存器的哪一个，哪2位？
    10. 99 / 4 = 24 ...... 3
    11. 商对应着寄存器的编号，(余数*8) 对应操作寄存器的最低位。
    12.  
    13. GICD_ITARGETSR24[25:24]  分配中断到不同的CPU接口中
    14.  
    15. 	写01 ： 分配给CPU接口0
    16. 	写10 ： 分配给CPU接口1
    17. 	写11 ： 分配给CPU接口0和CPU接口1
    18. 	
    19. 	这个寄存器的每1位管理一个CPU核，STM32MP1处理器有两个CPU核，因此需要两位即可
    20.

    2.5.9 GICC介绍

    2.5.10 GICC_CTLR ： GICC层全局使能寄存器

    2.5.11 GICC_PMR ： GICC层优先级屏蔽寄存器

    1. 如果一个中断信号的优先级值高于GICC_PMR寄存器字段中的值，则对应的中断将会被转发到CPU中，
    2. 中断信号的优先级通过GICD_IPRIORITYR寄存器进行配置。
    3.  
    4.  
    5. 假设中断信号的优先级为10， GICC_PMR[7:3]为20， 此中断信号被转发到CPU中。
    6. 假设中断信号的优先级为20， GICC_PMR[7:3]为10， 此中断信号不被转发到CPU中。

    2.5.12 GICC_IAR ： GICC层中断应答寄存器

    2.5.13 GICC_EOIR ：GICC层中断处理结束寄存器

    3、编写按键中断的驱动代码

    4、代码实现：

    4.1interrupt.c

    1. #include "../include/interrupt.h"
    2.  
    3. void hal_gpio_IT_init(gpio_t *gpios, unsigned int pins)
    4. {
    5. 	// 1. 使用GPIOF控制器的时钟
    6. 	RCC->MP_AHB4ENSETR = 0xFF;
    7. 	// 2. 设置PF9引脚为输入的功能
    8. 	gpios->MODER &= ~(0x3 << (pins * 2));
    9. }
    10. // KEY1->PF9->EXTI9-->输入事件编号为：9
    11. void hal_exti_IT_init(input_event_t input_event,
    12. 					  gpio_exti_t gpio_exti, trigger_t trigger)
    13. {
    14. 	// 1. 设置PF9连接到EXTI9上   EXTI_EXTICR3[15:8] = 0x5
    15. 	switch (input_event / 4)
    16. 	{
    17. 	case 0:
    18. 		EXTI->EXTICR1 &= ~(0xFF << (input_event % 4 * 8));
    19. 		EXTI->EXTICR1 |= (gpio_exti << (input_event % 4 * 8));
    20. 		break;
    21. 	case 1:
    22. 		EXTI->EXTICR2 &= ~(0xFF << (input_event % 4 * 8));
    23. 		EXTI->EXTICR2 |= (gpio_exti << (input_event % 4 * 8));
    24. 		break;
    25. 	case 2:
    26. 		EXTI->EXTICR3 &= ~(0xFF << (input_event % 4 * 8));
    27. 		EXTI->EXTICR3 |= (gpio_exti << (input_event % 4 * 8));
    28. 		break;
    29. 	case 3:
    30. 		EXTI->EXTICR4 &= ~(0xFF << (input_event % 4 * 8));
    31. 		EXTI->EXTICR4 |= (gpio_exti << (input_event % 4 * 8));
    32. 		break;
    33. 	}
    34. 	// 2. 设置KEY1按键为下降沿检测          EXTI_FTSR1[9] = 0x1
    35. 	if (trigger != RISING_TRIGGER)
    36. 	{
    37. 		EXTI->FTSR1 |= (0x1 << input_event);
    38. 	}
    39. 	else
    40. 	{
    41. 		EXTI->RTSR1 |= (0x1 << input_event);
    42. 	}
    43. 	// 3. 使能EXTI9中断                    EXTI_C1IMR1[9] = 0x1
    44. 	EXTI->C1IMR1 |= (0x1 << input_event);
    45. }
    46. // KEY1->PF9->EXTI9-->中断号为99
    47. void hal_gic_IT_init(unsigned int it_id, unsigned int pri)
    48. {
    49. 	// 1. 设置GICD层的中断使能   GICD_ISENABLER3[3] = 0x1
    50. 	GICD->ISENABLER[it_id / 32] |= (0x1 << (it_id % 32));
    51. 	// 2. 设置GICD层的中断优先级   GICD_IPRIORITYR24[31:27] = 自己定义 范围0-31
    52. 	GICD->IPRIORITYR[it_id / 4] &= ~(0x1F << (it_id % 4 * 8 + 3));
    53. 	GICD->IPRIORITYR[it_id / 4] |= (pri << (it_id % 4 * 8 + 3));
    54. 	// 3. 设置GICD层中断目标分配   GICD_ITARGETSR24[25:24] = 0x1
    55. 	GICD->ITARGETSR[it_id / 4] &= ~(0x3 << (it_id % 4 * 8));
    56. 	GICD->ITARGETSR[it_id / 4] |= (0x3 << (it_id % 4 * 8));
    57. 	// 4. 设置GICD层全局中断使能   GICD_CTLR[0] = 0x1
    58. 	GICD->CTRL |= (0x1 << 0);
    59. 	// 5. 设置GICC层中断优先级屏蔽 GICC_PMR[7:3] = 0x1F  自己也可以给其他值
    60. 	GICC->PMR |= (0x1F << 3);
    61. 	// 6. 设置GICC层全局中断使能   GICC_CTLR[0] = 0x1
    62. 	GICC->CTRL |= (0x1 << 0);
    63. }
    64.  
    65. void hal_clear_exti_IT(input_event_t input_event, trigger_t trigger)
    66. {
    67. 	if (trigger != RISING_TRIGGER)
    68. 	{
    69. 		EXTI->FPR1 |= (0x1 << input_event);
    70. 	}
    71. 	else
    72. 	{
    73. 		EXTI->RPR1 |= (0x1 << input_event);
    74. 	}
    75. }
    76.  
    77. void hal_clear_gic_IT(unsigned int it_id)
    78. {
    79. 	GICD->ICPENDR[it_id / 32] |= (0x1 << (it_id % 32));
    80. }

    4.2interrupt.h

    1. #ifndef __INTERRUPT_H__
    2. #define __INTERRUPT_H__
    3.  
    4. #include "stm32mp1xx_gpio.h"
    5. #include "stm32mp1xx_rcc.h"
    6. #include "stm32mp1xx_exti.h"
    7. #include "stm32mp1xx_gic.h"
    8. #include "gpio.h"
    9. typedef enum
    10. {
    11.     INPUT_ENENT_0 = 0,
    12.     INPUT_ENENT_1,
    13.     INPUT_ENENT_2,
    14.     INPUT_ENENT_3,
    15.     INPUT_ENENT_4,
    16.     INPUT_ENENT_5,
    17.     INPUT_ENENT_6,
    18.     INPUT_ENENT_7,
    19.     INPUT_ENENT_8,
    20.     INPUT_ENENT_9,
    21.     INPUT_ENENT_10,
    22.     INPUT_ENENT_11,
    23.     INPUT_ENENT_12,
    24.     INPUT_ENENT_13,
    25.     INPUT_ENENT_14,
    26.     INPUT_ENENT_15,
    27. } input_event_t;
    28.  
    29. typedef enum
    30. {
    31.     RISING_TRIGGER = 0,
    32.     FALLING_TRIGGER,
    33. } trigger_t;
    34. typedef enum
    35. {
    36.     GPIOA_EXTI = 0,
    37.     GPIOB_EXTI,
    38.     GPIOC_EXTI,
    39.     GPIOD_EXTI,
    40.     GPIOE_EXTI,
    41.     GPIOF_EXTI,
    42.     GPIOG_EXTI,
    43.     GPIOH_EXTI,
    44.     GPIOI_EXTI,
    45.     GPIOJ_EXTI,
    46. } gpio_exti_t;
    47.  
    48. void hal_gpio_IT_init(gpio_t *gpios, unsigned int pins);
    49.  
    50. void hal_exti_IT_init(input_event_t input_event,
    51.                       gpio_exti_t gpio_exti, trigger_t trigger);
    52.  
    53. void hal_gic_IT_init(unsigned int it_id, unsigned int pri);
    54.  
    55. void hal_clear_exti_IT(input_event_t input_event, trigger_t trigger);
    56.  
    57. void hal_clear_gic_IT(unsigned int it_id);
    58. #endif

    4.3gpio.h

    1. #ifndef __GPIO_H__
    2. #define __GPIO_H__
    3. #include "stm32mp1xx_gpio.h"
    4.  
    5. // 1. 封装RCC_MP_AHB4ENSETR寄存器，封装GPIOE，GPIOF寄存器
    6. #define RCC_MP_AHB4ENSETR (*(volatile unsigned int *)0x50000A28)
    7.  
    8. // 2. 封装LED灯控制的函数
    9. #define GPIO_PIN_0 0U
    10. #define GPIO_PIN_1 1U
    11. #define GPIO_PIN_2 2U
    12. #define GPIO_PIN_3 3U
    13. #define GPIO_PIN_4 4U
    14. #define GPIO_PIN_5 5U
    15. #define GPIO_PIN_6 6U
    16. #define GPIO_PIN_7 7U
    17. #define GPIO_PIN_8 8U
    18. #define GPIO_PIN_9 9U
    19. #define GPIO_PIN_10 10U
    20. #define GPIO_PIN_11 11U
    21. #define GPIO_PIN_12 12U
    22. #define GPIO_PIN_13 13U
    23. #define GPIO_PIN_14 14U
    24. #define GPIO_PIN_15 15U
    25. typedef enum
    26. {
    27.     GPIO_INPUT = 0,
    28.     GPIO_OUTPUT,
    29.     GPIO_AF,
    30.     GPIO_ANALOG,
    31. } gpio_mode_t; // gpio引脚模式的枚举类型
    32.  
    33. typedef enum
    34. {
    35.     GPIO_PP = 0,
    36.     GPIO_OD,
    37. } gpio_type_t; // gpio引脚的类型
    38.  
    39. typedef enum
    40. {
    41.     GPIO_LOW_SPEED = 0,
    42.     GPIO_MEDIUM_SPEED,
    43.     GPIO_HIGH_SPEED,
    44.     GPIO_VERY_HIGH_SPEED,
    45. } gpio_speed_t; // gpio引脚的速度
    46.  
    47. typedef enum
    48. {
    49.     GPIO_NO_PUPD = 0,
    50.     GPIO_UP,
    51.     GPIO_DOWN,
    52. } gpio_pupd_t;
    53.  
    54. typedef enum
    55. {
    56.     GPIO_RESET = 0,
    57.     GPIO_SET,
    58. } gpio_statues_t;
    59.  
    60. typedef struct
    61. {
    62.     unsigned int pins;  // 哪个引脚
    63.     gpio_mode_t mode;   // 引脚的模式
    64.     gpio_type_t type;   // 引脚的类型
    65.     gpio_speed_t speed; // 引脚的速度
    66.     gpio_pupd_t pupd;   // 引脚的上拉和下拉
    67. } gpio_init_t;          // gpio引脚初始化的结构体
    68.  
    69. /*
    70.     功能：GPIO引脚的初始化
    71.     参数：
    72.         gpios : 哪个组的gpio引脚
    73.         gpio_init : 引脚初始化的结构体
    74. */
    75. void hal_gpio_init(gpio_t *gpios, gpio_init_t *gpio_init);
    76. /*
    77.     功能：写gpio引脚的状态函数
    78.     参数：
    79.         gpios : 哪个组的gpio引脚
    80.         pins : 哪个引脚
    81.         statues : 引脚的状态
    82. */
    83. void hal_gpio_write(gpio_t *gpios, unsigned int pins, gpio_statues_t statues);
    84.  
    85. /*
    86.     功能：读gpio引脚状态的函数
    87.     参数：
    88.         gpios : 哪个组的gpio引脚
    89.         pins : 哪个引脚
    90.     返回值：
    91.         statues : 引脚的状态
    92. */
    93. gpio_statues_t hal_gpio_read(gpio_t *gpios, unsigned int pins);
    94.  
    95. void hal_gpio_toggle(gpio_t *gpios, unsigned int pins);
    96. #endif

    4.3stm32mp1xx_gpio.h

    1. #ifndef __STM32MP1xx_GPIO_H__
    2. #define __STM32MP1xx_GPIO_H__
    3.  
    4. typedef struct {
    5. 	volatile unsigned int MODER;   // 0x00
    6. 	volatile unsigned int OTYPER;  // 0x04
    7. 	volatile unsigned int OSPEEDR; // 0x08
    8. 	volatile unsigned int PUPDR;   // 0x0C
    9. 	volatile unsigned int IDR;     // 0x10
    10. 	volatile unsigned int ODR;     // 0x14
    11. 	volatile unsigned int BSRR;    // 0x18
    12. 	volatile unsigned int LCKR;    // 0x1C 
    13. 	volatile unsigned int AFRL;    // 0x20 
    14. 	volatile unsigned int AFRH;    // 0x24
    15. 	volatile unsigned int BRR;     // 0x28
    16. 	volatile unsigned int res;
    17. 	volatile unsigned int SECCFGR; // 0x30
    18.  
    19. }gpio_t;
    20.  
    21. #define  GPIOA   ((gpio_t *)0x50002000)
    22. #define  GPIOB   ((gpio_t *)0x50003000)
    23. #define  GPIOC   ((gpio_t *)0x50004000)
    24. #define  GPIOD   ((gpio_t *)0x50005000)
    25. #define  GPIOE   ((gpio_t *)0x50006000)
    26. #define  GPIOF   ((gpio_t *)0x50007000)
    27. #define  GPIOG   ((gpio_t *)0x50008000)
    28. #define  GPIOH   ((gpio_t *)0x50009000)
    29. #define  GPIOI   ((gpio_t *)0x5000A000)
    30. #define  GPIOJ   ((gpio_t *)0x5000B000)
    31. #define  GPIOK   ((gpio_t *)0x5000C000)
    32. #define  GPIOZ   ((gpio_t *)0x54004000)
    33.  
    34.  
    35. #endif // __STM32MP1xx_GPIO_H__

    4.4stm32mp1xx_rcc.h

    1. #ifndef __STM32MP1XX_RCC_H__
    2. #define __STM32MP1XX_RCC_H__ 
    3.  
    4. typedef struct {
    5. 	volatile unsigned int TZCR;     	// 0x000
    6. 	volatile unsigned int res1[2]; 		// 0x004-0x008
    7. 	volatile unsigned int OCENSETR;     // 0x00C
    8. 	volatile unsigned int OCENCLRR;  	// 0x010
    9. 	volatile unsigned int res2[1]; 		// 0x014
    10. 	volatile unsigned int HSICFGR; 		// 0x018
    11. 	volatile unsigned int CSICFGR; 		// 0x01C
    12. 	volatile unsigned int MPCKSELR; 	// 0x020
    13. 	volatile unsigned int ASSCKSELR; 	// 0x024
    14. 	volatile unsigned int PCK12SELR; 	// 0x028
    15. 	volatile unsigned int MPCKDIVR; 	// 0x02C
    16. 	volatile unsigned int AXIDIVR; 		// 0x030
    17. 	volatile unsigned int res3[2];      
    18. 	volatile unsigned int APB4DIVR; 	// 0x03C
    19. 	volatile unsigned int APB5DIVR; 	// 0x040
    20. 	volatile unsigned int RTCDIVR; 		// 0x044
    21. 	volatile unsigned int MSSCKSELR;    // 0x048
    22. 	volatile unsigned int res4[13];
    23. 	volatile unsigned int PLL1CR; 		// 0x080
    24. 	volatile unsigned int PLL1CFGR1; 	// 0x084
    25. 	volatile unsigned int PLL1CFGR2; 	// 0x088
    26. 	volatile unsigned int PLL1FRACR; 	// 0x08C
    27. 	volatile unsigned int PLL1CSGR;     // 0x090
    28. 	volatile unsigned int PLL2CR; 		// 0x094
    29. 	volatile unsigned int PLL2CFGR1; 	// 0x098
    30. 	volatile unsigned int PLL2CFGR2; 	// 0x09C
    31. 	volatile unsigned int PLL2FRACR;    // 0x0A0
    32. 	volatile unsigned int PLL2CSGR;     // 0x0A4
    33. 	volatile unsigned int res5[6];
    34. 	volatile unsigned int I2C46CKSELR;  // 0x0C0
    35. 	volatile unsigned int SPI6CKSELR;   // 0x0C4
    36. 	volatile unsigned int UART1CKSELR;  // 0x0C8
    37. 	volatile unsigned int RNG1CKSELR;   // 0x0CC
    38. 	volatile unsigned int CPERCKSELR;   // 0x0D0
    39. 	volatile unsigned int STGENCKSELR;  // 0x0D4
    40. 	volatile unsigned int DDRITFCR; 	// 0x0D8
    41. 	volatile unsigned int res6[9];
    42. 	volatile unsigned int MP_BOOTCR;  	// 0x100
    43. 	volatile unsigned int MP_SREQSETR;  // 0x104
    44. 	volatile unsigned int MP_SREQCLRR;  // 0x108
    45. 	volatile unsigned int MP_GCR;  		// 0x10C
    46. 	volatile unsigned int MP_APRSTCR; 	// 0x110 
    47. 	volatile unsigned int MP_APRSTSR;   // 0x114
    48. 	volatile unsigned int res7[10];
    49. 	volatile unsigned int BDCR; 		// 0x140
    50. 	volatile unsigned int RDLSICR;  	// 0x144
    51. 	volatile unsigned int res8[14];
    52. 	volatile unsigned int APB4RSTSETR; 	// 0x180
    53. 	volatile unsigned int APB4RSTCLRR; 	// 0x184
    54. 	volatile unsigned int APB5RSTSETR;  // 0x188
    55. 	volatile unsigned int APB5RSTCLRR;  // 0x18C
    56. 	volatile unsigned int AHB5RSTSETR;  // 0x190
    57. 	volatile unsigned int AHB5RSTCLRR;  // 0x194
    58. 	volatile unsigned int AHB6RSTSETR;  // 0x198
    59. 	volatile unsigned int AHB6RSTCLRR;  // 0x19C
    60. 	volatile unsigned int TZAHB6RSTSELR;// 0x1A0
    61. 	volatile unsigned int TZAHB6RSTCLRR;// 0x1A4
    62. 	volatile unsigned int res9[22];
    63. 	volatile unsigned int MP_APB4ENSETR;// 0x200
    64. 	volatile unsigned int MP_APB4ENCLRR;// 0x204
    65. 	volatile unsigned int MP_APB5ENSETR;// 0x208
    66. 	volatile unsigned int MP_APB5ENCLRR;// 0x20C
    67. 	volatile unsigned int MP_AHB5ENSETR;// 0x210
    68. 	volatile unsigned int MP_AHB5ENCLRR;// 0x214
    69. 	volatile unsigned int MP_AHB6ENSETR;// 0x218
    70. 	volatile unsigned int MP_AHB6ENCLRR;// 0x21C
    71. 	volatile unsigned int MP_TZAHB6ENSELR;// 0x220
    72. 	volatile unsigned int MP_TZAHB6ENCLRR;// 0x224
    73. 	volatile unsigned int res10[22];
    74. 	volatile unsigned int MC_APB4ENSETR; // 0x280
    75. 	volatile unsigned int MC_APB4ENCLRR; // 0x284
    76. 	volatile unsigned int MC_APB5ENSETR; // 0x288
    77. 	volatile unsigned int MC_APB5ENCLRR; // 0x28C
    78. 	volatile unsigned int MC_AHB5ENSETR; // 0x290
    79. 	volatile unsigned int MC_AHB5ENCLRR; // 0x294
    80. 	volatile unsigned int MC_AHB6ENSETR; // 0x298
    81. 	volatile unsigned int MC_AHB6ENCLRR; // 0x29C
    82. 	volatile unsigned int res11[24];
    83. 	volatile unsigned int MP_APB4LPENSETR; // 0x300
    84. 	volatile unsigned int MP_APB4LPENCLRR; // 0x304
    85. 	volatile unsigned int MP_APB5LPENSETR; // 0x308
    86. 	volatile unsigned int MP_APB5LPENCLRR; // 0x30C
    87. 	volatile unsigned int MP_AHB5LPENSETR; // 0x310
    88. 	volatile unsigned int MP_AHB5LPENCLRR; // 0x314
    89. 	volatile unsigned int MP_AHB6LPENSETR; // 0x318
    90. 	volatile unsigned int MP_AHB6LPENCLRR; // 0x31C
    91. 	volatile unsigned int MP_TZAHB6LPENSETR; // 0x320
    92. 	volatile unsigned int MP_TZAHB6LPENCLRR; // 0x324
    93. 	volatile unsigned int res12[22];
    94. 	volatile unsigned int MC_APB4LPENSETR; // 0x380
    95. 	volatile unsigned int MC_APB4LPENCLRR; // 0x384
    96. 	volatile unsigned int MC_APB5LPENSETR; // 0x388
    97. 	volatile unsigned int MC_APB5LPENCLRR; // 0x38C
    98. 	volatile unsigned int MC_AHB5LPENSETR; // 0x390
    99. 	volatile unsigned int MC_AHB5LPENCLRR; // 0x394
    100. 	volatile unsigned int MC_AHB6LPENSETR; // 0x398
    101. 	volatile unsigned int MC_AHB6LPENCLRR; // 0x39C
    102. 	volatile unsigned int res13[24];
    103. 	volatile unsigned int BR_RSTSCLRR; 		// 0x400
    104. 	volatile unsigned int MP_GRSTCSETR; 	// 0x404
    105. 	volatile unsigned int MP_RSTSR; 		// 0x408 
    106. 	volatile unsigned int MP_IWDGFZSETR; 	// 0x40C
    107. 	volatile unsigned int MP_IWDGFZCLRR;  	// 0x410
    108. 	volatile unsigned int MP_CIER; 			// 0x414
    109. 	volatile unsigned int MP_CIFR; 			// 0x418
    110. 	volatile unsigned int PWRLPDLYCR; 		// 0x41C
    111. 	volatile unsigned int MP_RSTSS; 		// 0x420
    112. 	volatile unsigned int res14[247];
    113. 	volatile unsigned int MCO1CFGR; 		// 0x800
    114. 	volatile unsigned int MCO2CFGR; 		// 0x804 
    115. 	volatile unsigned int OCRDYR; 			// 0x808
    116. 	volatile unsigned int DBGCFGR; 			// 0x80C
    117. 	volatile unsigned int res15[4];
    118. 	volatile unsigned int RCK3SELR; 		// 0x820
    119. 	volatile unsigned int RCK4SELR; 		// 0x824
    120. 	volatile unsigned int TIMG1PRER;  		// 0x828
    121. 	volatile unsigned int TIMG2PRER; 		// 0x82C
    122. 	volatile unsigned int MCUDIVR; 			// 0x830
    123. 	volatile unsigned int APB1DIVR; 		// 0x834
    124. 	volatile unsigned int APB2DIVR; 		// 0x838
    125. 	volatile unsigned int APB3DIVR; 		// 0x83C
    126. 	volatile unsigned int res16[16];
    127. 	volatile unsigned int PLL3CR;   		// 0x880
    128. 	volatile unsigned int PLL3CFGR1; 		// 0x884
    129. 	volatile unsigned int PLL3CFGR2; 		// 0x888
    130. 	volatile unsigned int PLL3FRACR; 		// 0x88C
    131. 	volatile unsigned int PLL3CSGR; 		// 0x890
    132. 	volatile unsigned int PLL4CR; 			// 0x894
    133. 	volatile unsigned int PLL4CFGR1; 		// 0x898
    134. 	volatile unsigned int PLL4CFGR2; 		// 0x89C
    135. 	volatile unsigned int PLL4FRACR; 		// 0x8A0
    136. 	volatile unsigned int PLL4CSGR; 		// 0x8A4
    137. 	volatile unsigned int res17[6];
    138. 	volatile unsigned int I2C12CKSELR; 		// 0x8C0
    139. 	volatile unsigned int I2C35CKSELR;  	// 0x8C4
    140. 	volatile unsigned int SAI1CKSELR; 		// 0x8C8
    141. 	volatile unsigned int SAI2CKSELR; 		// 0x8CC
    142. 	volatile unsigned int SAI3CKSELR; 		// 0x8D0
    143. 	volatile unsigned int SAI4CKSELR; 		// 0x8D4
    144. 	volatile unsigned int SPI2S1CKSELR; 	// 0x8D8
    145. 	volatile unsigned int SPI2S23CKSELR; 	// 0x8DC
    146. 	volatile unsigned int SPI45CKSELR; 		// 0x8E0
    147. 	volatile unsigned int UART6CKSELR; 		// 0x8E4
    148. 	volatile unsigned int UART24CKSELR; 	// 0x8E8
    149. 	volatile unsigned int UART35CKSELR; 	// 0x8EC
    150. 	volatile unsigned int UART78CKSELR; 	// 0x8F0
    151. 	volatile unsigned int SDMMC12CKSELR; 	// 0x8F4
    152. 	volatile unsigned int SDMMC3CKSELR; 	// 0x8F8
    153. 	volatile unsigned int ETHCKSELR; 		// 0x8FC
    154. 	volatile unsigned int QSPICKSELR; 		// 0x900
    155. 	volatile unsigned int FMCCKSELR; 		// 0x904
    156. 	volatile unsigned int res18[1];
    157. 	volatile unsigned int FDCANCKSELR; 		// 0x90C
    158. 	volatile unsigned int res19[1];
    159. 	volatile unsigned int SPDIFCKSELR; 		// 0x914
    160. 	volatile unsigned int CECCKSELR; 		// 0x918
    161. 	volatile unsigned int USBCKSELR; 		// 0x91C
    162. 	volatile unsigned int RNG2CKSELR;  		// 0x920
    163. 	volatile unsigned int DSICKSELR; 		// 0x924
    164. 	volatile unsigned int ADCCKSELR; 		// 0x928
    165. 	volatile unsigned int LPTIM45CKSELR; 	// 0x92C
    166. 	volatile unsigned int LPTIM23CKSELR;    // 0x930
    167. 	volatile unsigned int LPTIM1CKSELR; 	// 0x934
    168. 	volatile unsigned int res20[18];
    169. 	volatile unsigned int APB1RSTSETR; 		// 0x980
    170. 	volatile unsigned int APB1RSTCLRR; 		// 0x984
    171. 	volatile unsigned int APB2RSTSETR; 		// 0x988
    172. 	volatile unsigned int APB2RSTCLRR; 		// 0x98C
    173. 	volatile unsigned int APB3RSTSETR; 		// 0x990
    174. 	volatile unsigned int APB3RSTCLRR; 		// 0x994
    175. 	volatile unsigned int AHB2RSTSETR; 		// 0x998
    176. 	volatile unsigned int AHB2RSTCLRR;  	// 0x99C
    177. 	volatile unsigned int AHB3RSTSETR; 		// 0x9A0
    178. 	volatile unsigned int AHB3RSTCLRR; 		// 0x9A4
    179. 	volatile unsigned int AHB4RSTSETR; 		// 0x9A8
    180. 	volatile unsigned int AHB4RSTCLRR; 		// 0x9AC
    181. 	volatile unsigned int res21[20];
    182. 	volatile unsigned int MP_APB1ENSETR; 	// 0xA00
    183. 	volatile unsigned int MP_APB1ENCLRR; 	// 0xA04
    184. 	volatile unsigned int MP_APB2ENSETR; 	// 0xA08
    185. 	volatile unsigned int MP_APB2ENCLRR;  	// 0xA0C
    186. 	volatile unsigned int MP_APB3ENSETR; 	// 0xA10
    187. 	volatile unsigned int MP_APB3ENCLRR; 	// 0xA14
    188. 	volatile unsigned int MP_AHB2ENSETR; 	// 0xA18
    189. 	volatile unsigned int MP_AHB2ENCLRR; 	// 0xA1C
    190. 	volatile unsigned int MP_AHB3ENSETR; 	// 0xA20
    191. 	volatile unsigned int MP_AHB3ENCLRR; 	// 0xA24
    192. 	volatile unsigned int MP_AHB4ENSETR; 	// 0xA28
    193. 	volatile unsigned int MP_AHB4ENCLRR; 	// 0xA2C
    194. 	volatile unsigned int res22[2];
    195. 	volatile unsigned int MP_MLAHBENSETR; 	// 0xA38
    196. 	volatile unsigned int MP_MLAHBENCLRR; 	// 0xA3C
    197. 	volatile unsigned int res23[16];
    198. 	volatile unsigned int MC_APB1ENSETR; 	// 0xA80
    199. 	volatile unsigned int MC_APB1ENCLRR; 	// 0xA84
    200. 	volatile unsigned int MC_APB2ENSETR; 	// 0xA88
    201. 	volatile unsigned int MC_APB2ENCLRR; 	// 0xA8C
    202. 	volatile unsigned int MC_APB3ENSETR; 	// 0xA90
    203. 	volatile unsigned int MC_APB3ENCLRR; 	// 0xA94
    204. 	volatile unsigned int MC_AHB2ENSETR; 	// 0xA98
    205. 	volatile unsigned int MC_AHB2ENCLRR; 	// 0xA9C
    206. 	volatile unsigned int MC_AHB3ENSETR; 	// 0xAA0
    207. 	volatile unsigned int MC_AHB3ENCLRR; 	// 0xAA4
    208. 	volatile unsigned int MC_AHB4ENSETR; 	// 0xAA8
    209. 	volatile unsigned int MC_AHB4ENCLRR; 	// 0xAAC
    210. 	volatile unsigned int MC_AXIMENSETR; 	// 0xAB0
    211. 	volatile unsigned int MC_AXIMENCLRR; 	// 0xAB4
    212. 	volatile unsigned int MC_MLAHBENSETR; 	// 0xAB8
    213. 	volatile unsigned int MC_MLAHBENCLRR; 	// 0xABC
    214. 	volatile unsigned int res24[16];
    215. 	volatile unsigned int MP_APB1LPENSETR; 	// 0xB00
    216. 	volatile unsigned int MP_APB1LPENCLRR; 	// 0xB04
    217. 	volatile unsigned int MP_APB2LPENSETR;  // 0xB08
    218. 	volatile unsigned int MP_APB2LPENCLRR; 	// 0xB0C
    219. 	volatile unsigned int MP_APB3LPENSETR; 	// 0xB10
    220. 	volatile unsigned int MP_APB3LPENCLRR;  // 0xB14
    221. 	volatile unsigned int MP_AHB2LPENSETR;  // 0xB18
    222. 	volatile unsigned int MP_AHB2LPENCLRR;  // 0xB1C
    223. 	volatile unsigned int MP_AHB3LPENSETR;  // 0xB20
    224. 	volatile unsigned int MP_AHB3LPENCLRR;  // 0xB24
    225. 	volatile unsigned int MP_AHB4LPENSETR;  // 0xB28
    226. 	volatile unsigned int MP_AHB4LPENCLRR;  // 0xB2C
    227. 	volatile unsigned int MP_AXIMLPENSETR;  // 0xB30
    228. 	volatile unsigned int MP_AXIMLPENCLRR;  // 0xB34
    229. 	volatile unsigned int MP_MLAHBLPENSETR; // 0xB38
    230. 	volatile unsigned int MP_MLAHBLPENCLRR; // 0xB3C
    231. 	volatile unsigned int res25[16];
    232. 	volatile unsigned int MC_APB1LPENSETR;  // 0xB80
    233. 	volatile unsigned int MC_APB1LPENCLRR; 	// 0xB84
    234. 	volatile unsigned int MC_APB2LPENSETR;  // 0xB88
    235. 	volatile unsigned int MC_APB2LPENCLRR;  // 0xB8C
    236. 	volatile unsigned int MC_APB3LPENSETR;  // 0xB90 
    237. 	volatile unsigned int MC_APB3LPENCLRR;  // 0xB94
    238. 	volatile unsigned int MC_AHB2LPENSETR;  // 0xB98
    239. 	volatile unsigned int MC_AHB2LPENCLRR;  // 0xB9C
    240. 	volatile unsigned int MC_AHB3LPENSETR;  // 0xBA0 
    241. 	volatile unsigned int MC_AHB3LPENCLRR;  // 0xBA4
    242. 	volatile unsigned int MC_AHB4LPENSETR;  // 0xBA8
    243. 	volatile unsigned int MC_AHB4LPENCLRR;  // 0xBAC
    244. 	volatile unsigned int MC_AXIMLPENSETR;  // 0xBB0
    245. 	volatile unsigned int MC_AXIMLPENCLRR;  // 0xBB4
    246. 	volatile unsigned int MC_MLAHBLPENSETR; // 0xBB8
    247. 	volatile unsigned int MC_MLAHBLPENCLRR; // 0xBBC
    248. 	volatile unsigned int res26[16];
    249. 	volatile unsigned int MC_RSTSCLRR;  	// 0xC00
    250. 	volatile unsigned int res27[4];
    251. 	volatile unsigned int MC_CIER;  		// 0xC14
    252. 	volatile unsigned int MC_CIFR; 			// 0xC18
    253. 	volatile unsigned int res28[246];
    254. 	volatile unsigned int VERR; 			// 0xFF4
    255. 	volatile unsigned int IDR; 				// 0xFF8
    256. 	volatile unsigned int SIDR; 			// 0xFFC
    257. }rcc_t;
    258.  
    259. #define RCC   ((rcc_t *)0x50000000)
    260.  
    261. #endif  // __STM32MP1XX_RCC_H__

    4.5stm32mp1xx_exti.h

    1. #ifndef __STM32MP1XX_EXTI_H__
    2. #define __STM32MP1XX_EXTI_H__
    3.  
    4. typedef struct{
    5. 	volatile unsigned int RTSR1; 	// EXTI rising trigger selection register 	
    6. 	volatile unsigned int FTSR1; 	// EXTI falling trigger selection register	
    7. 	volatile unsigned int SWIER1;   // EXTI software interrupt event register 
    8. 	volatile unsigned int RPR1;     // EXTI rising edge pending register
    9. 	volatile unsigned int FPR1;  	// EXTI falling edge pending register
    10. 	volatile unsigned int TZENR1;   // EXTI TrustZone enable register
    11. 	volatile unsigned int RES1[2];  
    12. 	volatile unsigned int RTSR2;    // EXTI rising trigger selection register
    13. 	volatile unsigned int FTSR2;    // EXTI falling trigger selection register
    14. 	volatile unsigned int SWIER2;   // EXTI software interrupt event register
    15. 	volatile unsigned int RPR2;     // EXTI rising edge pending register
    16. 	volatile unsigned int FPR2;	    // EXTI falling edge pending register
    17. 	volatile unsigned int TZENR2;   // EXTI TrustZone enable register
    18. 	volatile unsigned int RES2[2];
    19. 	volatile unsigned int RTSR3;    // EXTI rising trigger selection register
    20. 	volatile unsigned int FTSR3;    // EXTI falling trigger selection register
    21. 	volatile unsigned int SWIER3;   // EXTI software interrupt event register
    22. 	volatile unsigned int RPR3;     // EXTI rising edge pending register
    23. 	volatile unsigned int FPR3;     // EXTI falling edge pending register
    24. 	volatile unsigned int TZENR3;   // EXTI TrustZone enable register
    25. 	volatile unsigned int RES3[2];
    26. 	volatile unsigned int EXTICR1;	// EXTI external interrupt selection register 1
    27. 	volatile unsigned int EXTICR2;  // EXTI external interrupt selection register 2	
    28. 	volatile unsigned int EXTICR3;  // EXTI external interrupt selection register 3	
    29. 	volatile unsigned int EXTICR4;  // EXTI external interrupt selection register 4	
    30. 	volatile unsigned int RES4[4];
    31. 	volatile unsigned int C1IMR1;   // EXTI CPU1 wakeup with interrupt mask register
    32. 	volatile unsigned int C1EMR1;   // EXTI CPU1 wakeup with event mask register
    33. 	volatile unsigned int RES5[2];
    34. 	volatile unsigned int C1IMR2;   // EXTI CPU1 wakeup with interrupt mask register
    35. 	volatile unsigned int C1EMR2;   // EXTI CPU1 wakeup with event mask register
    36. 	volatile unsigned int RES6[2];
    37. 	volatile unsigned int C1IMR3;   // EXTI CPU1 wakeup with interrupt mask register	
    38. 	volatile unsigned int C1EMR3;   // EXTI CPU1 wakeup with event mask register 
    39. 	volatile unsigned int RES7[6];
    40. 	volatile unsigned int C2IMR1;   // EXTI CPU2 wakeup with interrupt mask register
    41. 	volatile unsigned int C2EMR1;   // EXTI CPU2 wakeup with event mask register
    42. 	volatile unsigned int RES8[2];
    43. 	volatile unsigned int C2IMR2;   // EXTI CPU2 wakeup with interrupt mask register
    44. 	volatile unsigned int C2EMR2;   // EXTI CPU2 wakeup with event mask register
    45. 	volatile unsigned int RES9[2];
    46. 	volatile unsigned int C2IMR3;   // EXTI CPU2 wakeup with interrupt mask register 
    47. 	volatile unsigned int C2EMR3;   // EXTI CPU2 wakeup with event mask register 
    48. 	volatile unsigned int RES10[2];
    49. }exti_t;
    50.  
    51. #define  EXTI   ((exti_t*)0x5000D000)
    52.  
    53. #endif //__STM32MP1XX_EXTI_H__

    4.6stm32mp1xx_gic.h

    1. #ifndef __STM32MP1XX_GIC_H__
    2. #define __STM32MP1XX_GIC_H__ 
    3.  
    4.  
    5. typedef struct {
    6. 	volatile unsigned int CTRL;
    7. 	volatile unsigned int TYPER;
    8. 	volatile unsigned int IIDR;
    9. 	volatile unsigned int RES1[29];
    10. 	volatile unsigned int IGROUPR[9];
    11. 	volatile unsigned int RES2[23];
    12. 	volatile unsigned int ISENABLER[9];
    13. 	volatile unsigned int RES3[23];
    14. 	volatile unsigned int ICENABLER[9];
    15. 	volatile unsigned int RES4[23];
    16. 	volatile unsigned int ISPENDR[9];
    17. 	volatile unsigned int RES5[23];
    18. 	volatile unsigned int ICPENDR[9];
    19. 	volatile unsigned int RES6[23];
    20. 	volatile unsigned int ISACTIVER[9];
    21. 	volatile unsigned int RES7[23];
    22. 	volatile unsigned int ICACTIVER[9];
    23. 	volatile unsigned int RES8[23];
    24. 	volatile unsigned int IPRIORITYR[72];
    25. 	volatile unsigned int RES9[184];
    26. 	volatile unsigned int ITARGETSR[72];
    27. 	volatile unsigned int RES10[184];	
    28. 	volatile unsigned int ICFGR[18];
    29. 	volatile unsigned int RES11[46];
    30.  
    31. }gicd_t;
    32. #define GICD  ((gicd_t*)0xA0021000)
    33.  
    34.  
    35. typedef struct {
    36. 	volatile unsigned int CTRL;
    37. 	volatile unsigned int PMR;
    38. 	volatile unsigned int BRR;
    39. 	volatile unsigned int IAR;
    40. 	volatile unsigned int EOIR;
    41. 	volatile unsigned int RPR;
    42. 	volatile unsigned int HPPIR;
    43. 	volatile unsigned int ABPR;
    44. 	volatile unsigned int AIAR;
    45. 	volatile unsigned int AEOIR;
    46. 	volatile unsigned int AHPPIR;
    47. 	volatile unsigned int RES1[41];
    48. 	volatile unsigned int APR0;
    49. 	volatile unsigned int RES2[3];
    50. 	volatile unsigned int NSAPR0;
    51. 	volatile unsigned int RES3[6];
    52. 	volatile unsigned int IIDR;
    53. 	volatile unsigned int RES4[960];
    54. 	volatile unsigned int DIRDIR;
    55.  
    56. }gicc_t;
    57. #define GICC  ((gicc_t*)0xA0022000) 
    58.  
    59. #endif  // __STM32MP1XX_GIC_H__

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  • 原文地址：https://blog.csdn.net/a2998658795/article/details/126688096