xilinx xdc 约束及时序收敛分析

 

Clock Modifying Blocks (CMBs) 模块Vivado会自动生成时钟约束：

 

 

 

 无效主时钟：ug906 page283

常用时序分析命令：

//显示最差的前50个路径

report_design_analysis -max_paths 50 -setup -show_all

report_timing -max_paths 50 -setup -input_pins -name worstSetupPaths

report_timing -max_paths 100 -nworst 100 -unique_pins

### Report the high fanout net

report_high_fanout_nets -load_types -max_nets 100

### Report timing through specific high fanout net

report_timing -through [get_nets I_GLOBAL_RST_N_i] -name high_fanout_1

report_design_analysis -congestion

report_compile_order -constraints

 

 

 

set_max_delay使用-datapath_only后hold的检查就会flase掉即忽略，如果不加该参数则不影响hold检查。

 

 

 

 

 

 

 

 

参考：

UG903

UG904

c_ug949-vivado-design-methodology

Design Analysis and Closure Techniques (UG906)

Constraining Designs for Synthesis and Timing Analysis.pdf

Static Timing Analysis for Nanometer Designs.pdf

Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints.pdf