极简UVM RAL示例(PART2--通过rsp返回给regmodel)

为了让RAL使用rsp来返回read结果，做如下修改。

变化点1:driver

相对于part1，driver改用put_response(rsp)

代码

class driver extends uvm_driver #(reg_tr);
virtual reg_if drv_if;
`uvm_component_utils(driver)
function new(string name=“”,uvm_component parent=null);
super.new(name,parent);
endfunction
extern virtual function void build_phase(uvm_phase phase);
extern task main_phase(uvm_phase phase);
endclass

function void driver::build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_db#(virtual reg_if)::get(this,“”,“drv_if”,drv_if);

endfunction

task driver::main_phase(uvm_phase phase);
drv_if.wr <= 1’b0;
drv_if.rd <= 1’b0;
drv_if.din <= 0;
drv_if.addr <= 0;
@(posedge drv_if.rstn);
while(1) begin
seq_item_port.get_next_item(req);
rsp = new(“rsp”);
rsp.set_id_info(req);
rsp.wr = req.wr;
rsp.rd = req.rd;
rsp.addr = req.addr;
rsp.din = req.din;
//drive access
@(drv_if.cb);
drv_if.addr <= req.addr;
if(req.wr) begin
drv_if.wr <= 1’b1;
drv_if.din <= req.din;
@(drv_if.cb);
drv_if.wr <= 1’b0;
end
if(req.rd) begin
drv_if.rd <= 1’b1;
@(drv_if.cb);
rsp.dout <= drv_if.dout;
drv_if.rd <= 1’b0;
end
@(drv_if.cb);
seq_item_port.put_response(rsp);
seq_item_port.item_done();
end
endtask

变化点2: class tests

相对于part1，tests 增加配置provides_responses = 1’b1;

代码

adp = new("adp");
adp.provides_responses = 1'b1;
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