--加法器(Adder):考虑进位溢出
assign o_sum[DATA_WIDTH:0] = i_parta[DATA_WIDTH-1:0] + i_partb[DATA_WIDTH-1:0];
--半加器(Half-Adder)(DATA_WIDTH == 1):没有进位输入(DATA_WIDTH == 1)
assign {o_carry, o_sum[DATA_WIDTH-1:0]} = i_parta[DATA_WIDTH-1:0] + i_partb[DATA_WIDTH-1:0];
--全加器(Full-Adder)(DATA_WIDTH == 1):存在进位输入(DATA_WIDTH == 1)
assign {o_carry, o_sum[DATA_WIDTH-1:0]} = i_parta[DATA_WIDTH-1:0] + i_partb[DATA_WIDTH-1:0] + i_carry;
比较器(Comparator)
assign equal = (compa == compb) ? 1'b1 : 1'b0;
assign bigger = (compa >= compb) ? 1'b1 : 1'b0;
assign smaller = (compa <= compb) ? 1'b1 : 1'b0;
选择器(Selector)(Arbiter)(Multiplexor)(MUX)
// 简单的给出了三种实现方式:
// 方式1:
assign result = sel ? dina : dinb;
// 方式2:
assign result = ({(DATA_WIDTH){sel}} & dina[D