cadence virtuoso layout drc error

问题：

The BORDER layer must enclose all chip layout patterns, which all chip layout patterns include seal ring if seal ring has been added by designers.
This rule checking includes the layers of DNW,AA,NW,NC,PC,MVN, MVP,DG,GT,SN,SP,SAB,CT,M1,V1,Mn,Vn,P2,TMn,TVn,PA,MD,Fuse,ALPA,AADUM, GTDUM, MnDUM, TMnDUM.

解决办法：

在图层中找到BORDER层，画一个的矩形把整个版图框起来即可。

如图中的黄色框。

但是一般底层版图不用管这个问题，到了TOP层再画矩形框起来就行了。