g/s reset && Register test

Any chip must envolve using reset and Register;
Maybe different IC company has different view about reset;
But Register almost have same usage; such Types: RW,RO,WO,RWONE,RC;
Register will be classed into two kinds: configured reg and no-figured reg(not viewed on regdb or datasheet);

1 Reset

In the company that i work now, reset will be used by srstn and grstn;
a. grstn–low active
when grstn is low,All the configured register by software will be initialed to default value; this envolves RW,RO type reg;
b. srstn–low active
when srstn is low,Reset all the no-configured reg,Including hardware status reg,fifo,station machione status initialed;

Verification plan:
1.Chip auto poweron flow: when po_rstn is high,then grst and rstn will be high at the same time;
2.up grstn,config reg,tehn up srstn,final data flow; ----Normal case config flow
3.up srstn,then up grstn,then config reg,to check whether it affects dut or not;
4.When data flow run,only low srst,to check whether fifo is empty,logic is initialed, then up high srstn,to check whether dut can work or not;
5.When data flow run,only low grstn,then up grstn,then config reg,to check whther dut is working or not;
6.wehn data flow is ended–ensure fifo is empty too;only low srst to check statistics and state initialed;
7.when data flow is ended–ensure fifo is empty too; only low grstn,to check configured reg is initialed;

2 Register–regdb

1.Register attributes scan test
uvm buillt-in test: uvm_reg_access_seq;uvm_reg_hw_reset_seq;uvm_reg_bit_bash_seq;
In teh beginnning: Must use uvm_front_door to check; after ,use uvm_backdorr to speed up config reg;
2.RW Reg test
1.By using function case to config ,then to test; check monitor’s result with refmdl’s result;
2.dynamatic change reg;
3.RO reg test–uploaded reg
4.Anormal reg test
Visit invalied address reg and reserved filed reg to check dut is not hang; and reserved filed data is default value;