• AXI-Stream协议详解（3）—— AXI4-Stream IP核原理分析

    一、前言

            在之前的文章中，我们介绍了AXI-S协议的一些基础知识，这是我们进行本文学习的前置基础，因此建议在开始本文章的学习前，完整阅读以下两篇文章：

    AXI-Stream协议详解（1）—— Introductionicon-default.png?t=N7T8https://blog.csdn.net/apple_53311083/article/details/134058532?spm=1001.2014.3001.5501AXI-Stream协议详解（2）—— Interface Signalsicon-default.png?t=N7T8https://blog.csdn.net/apple_53311083/article/details/134065597?spm=1001.2014.3001.5501

    二、带AXI-Stream接口的IP核

    1、IP核创建

            在这里我们选择最底下的一项，创建一个带有AXI接口的IP核

            接下来我们设置IP核的一些细节信息，这里把名称改成了axis_m，代表这是AXI-Stream协议的主机。

            选择stream协议，选择主机类型，相应地完成名称更改，这里的数据位宽我们暂时不做更改，保持默认的32bit就行。

            最后这里直接添加到IP库里就完成了。

            然后我们通过同样的方式可以完成axi_s（带有AXI-S接口的从机）的创建，这里就省略创建过程了。

    2、IP核学习

            在IP Catlog下搜索找到我们之前创建的2个带有AXI-Stream协议的IP核

            右击选择Edit in packager

            我们先以从机为例，显示如何找到AXI-S的设计部分，直接点击OK直到打开一个新的vivado界面

            可以看到里面有两个模块 

     

            我们依次打开两个文件，同时可以把axis_m IP核中的文件同时打开，方便我们进行学习，打开过程同上，这里不做重复。

            对于axis_s_v1_0和axis_m_v1_0这两个模块来说，只是完成了对底层模块的一个例化，所以没有什么可以过多赘述的。

            下面我们着重介绍axis_s_v1_0_S00_AXIS和axis_m_v1_0_M00_AXIS两个模块

    三、AXI-Stream源代码学习

            其实Xilinx官方已经给出了非常详细的英文注释，可以帮助我们快速了解整个AXI-S协议的实现方式，写的真的非常好。这里也只是在其基础上做一个简单的翻译和补充，首先给出笔者中文注释版本，再给出官方的注释版本，推荐阅读后者。

    1、AXIS主机部分

    1.1 中文注释

    1.  
    2. `timescale 1 ns / 1 ps
    3.  
    4. 	module axis_m_v1_0_M00_AXIS #
    5. 	(
    6. 		/*
    7. 			用户可以在此自定义参数
    8. 		*/
    9. 		
    10. 		parameter integer C_M_AXIS_TDATA_WIDTH	= 32,      // 发送数据的位宽
    11. 		// 初始化的最大计数时钟（等待系统稳定的时间）
    12. 		parameter integer C_M_START_COUNT	= 32
    13. 	)
    14. 	(
    15. 		/*
    16. 			用户可以在此自定义端口
    17. 		*/
    18.  
    19. 		//全局信号
    20. 		input wire  M_AXIS_ACLK,                    			     // 时钟信号
    21. 		input wire  M_AXIS_ARESETN,                   				 // 复位信号（低电平有效）
    22.  
    23. 		output wire  M_AXIS_TVALID,                   				 //有效信号，代表主机已经准备好了
    24. 		output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,       //数据信号
    25. 		output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,	 //数据修饰符，辨别字节类型	
    26. 		output wire  M_AXIS_TLAST,                      		     //last信号，拉高代表是传输中的最后一个字节
    27. 		input wire  M_AXIS_TREADY                                    //ready信号，代表从机准备好了
    28. 	);
    29.                                               
    30. 	localparam NUMBER_OF_OUTPUT_WORDS = 8;                           //发送数据的个数                                        
    31. 	                                                                                     
    32. 	//函数：以2为低求对数，用于计算位宽
    33. 	function integer clogb2 (input integer bit_depth);                                   
    34. 	  begin                                                                              
    35. 	    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                                      
    36. 	      bit_depth = bit_depth >> 1;                                                    
    37. 	  end                                                                                
    38. 	endfunction                                                                          
    39. 	                                                                                                                    
    40. 	localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);  //等待计时寄存器的位宽                      
    41. 	localparam bit_num  = clogb2(NUMBER_OF_OUTPUT_WORDS);            //发送数据寄存器位宽                 
    42. 	                                                                                          
    43. 	//状态机参数                              
    44. 	parameter [1:0] IDLE = 2'b00,         						     //初始状态                                                                                               
    45. 	                INIT_COUNTER  = 2'b01,                           //初始化计数器，等待计数值达到最大计数时钟，进入下一个状态
    46. 	                SEND_STREAM   = 2'b10;                           //数据发送状态
    47.                                                                     
    48. 	reg [1:0] mst_exec_state;                                        //状态寄存器                                                                                                       
    49. 	reg [bit_num-1:0] read_pointer;                                  //FIFO读指针                          
    51. 	// AXIS内部信号
    52. 	reg [WAIT_COUNT_BITS-1 : 0] 	count;                           //等待计数器（实现我们之前说的计时功能）
    53. 	wire  	axis_tvalid;                                             //valid
    54. 	reg  	axis_tvalid_delay;                                       //延时一个时钟周期的valid
    55. 	wire  	axis_tlast;                                              //last
    56. 	reg  	axis_tlast_delay;                                        //延迟一个时钟周期的last
    58. 	reg [C_M_AXIS_TDATA_WIDTH-1 : 0] 	stream_data_out;             //data
    59. 	wire  	tx_en;                                                   //发送使能
    60. 	reg  	tx_done;                                                 //发送完成
    63. 	//赋值操作
    64. 	assign M_AXIS_TVALID	= axis_tvalid_delay;                    
    65. 	assign M_AXIS_TDATA	= stream_data_out;
    66. 	assign M_AXIS_TLAST	= axis_tlast_delay;
    67. 	assign M_AXIS_TSTRB	= {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};         //全1 
    68.  
    69.  
    70. 	//控制状态机                          
    71. 	always @(posedge M_AXIS_ACLK)                                             
    72. 	begin                                                                     
    73. 	  if (!M_AXIS_ARESETN)                                                                                           
    74. 	    begin                                                                 
    75. 	      mst_exec_state <= IDLE;                                             
    76. 	      count    <= 0;                                                      
    77. 	    end                                                                   
    78. 	  else                                                                    
    79. 	    case (mst_exec_state)                                                 
    80. 	      IDLE:                                             //一个周期后直接进入下一个状态                                                                                                              
    81. 	            mst_exec_state  <= INIT_COUNTER;                                                                                                                                                             
    82. 	      INIT_COUNTER:                                     //计数器达到最大计数值，进入次态                                                         
    83. 	        if ( count == C_M_START_COUNT - 1 )                               
    84. 	          begin                                                           
    85. 	            mst_exec_state  <= SEND_STREAM;                               
    86. 	          end                                                             
    87. 	        else                                                              
    88. 	          begin                                                           
    89. 	            count <= count + 1;                                           
    90. 	            mst_exec_state  <= INIT_COUNTER;                              
    91. 	          end                                                             
    92. 	                                                                          
    93. 	      SEND_STREAM:                                    //发送状态，完成发送后回到初始态                                         
    94. 	        if (tx_done)                                                      
    95. 	          begin                                                           
    96. 	            mst_exec_state <= IDLE;                                       
    97. 	          end                                                             
    98. 	        else                                                              
    99. 	          begin                                                           
    100. 	            mst_exec_state <= SEND_STREAM;                                
    101. 	          end                                                             
    102. 	    endcase                                                               
    103. 	end                                                                       
    104.  
    105. 	//valid信号（表示主机有没有准备好），当处于发送状态，读指针小于发送数据个数时（也就是处于发送状态且还有数据要发）生效
    106. 	assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
    107. 	                                                                                               
    108. 	//last信号（表示发送的最后一个字节），当读指针等于发送数据个数-1时生效
    109. 	assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);                                
    110. 	                                                                                               
    111. 	//完成axis_tvalid_delay，axis_tlast_delay（延迟一个时钟的valid和last）的赋值
    112. 	always @(posedge M_AXIS_ACLK)                                                                  
    113. 	begin                                                                                          
    114. 	  if (!M_AXIS_ARESETN)                                                                         
    115. 	    begin                                                                                      
    116. 	      axis_tvalid_delay <= 1'b0;                                                               
    117. 	      axis_tlast_delay <= 1'b0;                                                                
    118. 	    end                                                                                        
    119. 	  else                                                                                         
    120. 	    begin                                                                                      
    121. 	      axis_tvalid_delay <= axis_tvalid;                                                        
    122. 	      axis_tlast_delay <= axis_tlast;                                                          
    123. 	    end                                                                                        
    124. 	end                                                                                            
    125.  
    126. 	//读指针
    127. 	always@(posedge M_AXIS_ACLK)                                               
    128. 	begin                                                                             
    129. 	  if(!M_AXIS_ARESETN)                                //复位                                             
    130. 	    begin                                                                        
    131. 	      read_pointer <= 0;                                                         
    132. 	      tx_done <= 1'b0;                                                           
    133. 	    end                                                                          
    134. 	  else                                                                           
    135. 	    if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)    //读指针小于等于发送数据个数-1，如果tx_en(发送使能)，读指针递增，发送完成信号为0                             
    136. 	      begin                                                                      
    137. 	        if (tx_en)                                                                                               
    138. 	          begin                                                                  
    139. 	            read_pointer <= read_pointer + 1;                                    
    140. 	            tx_done <= 1'b0;                                                     
    141. 	          end                                                                    
    142. 	      end                                                                        
    143. 	    else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)                             
    144. 	      begin                                                                                                                            
    145. 	        tx_done <= 1'b1;                             //如果读指针等于发送数据个数，完成信号为1                                  
    146. 	      end                                                                        
    147. 	end                                                                              
    149. 	assign tx_en = M_AXIS_TREADY && axis_tvalid;      	//读使能信号（从机+主机准备好）
    150. 	                                                     
    151. 	    //生成数据输出      
    152. 	    always @( posedge M_AXIS_ACLK )                  
    153. 	    begin                                            
    154. 	      if(!M_AXIS_ARESETN)                            
    155. 	        begin                                        
    156. 	          stream_data_out <= 1;                      
    157. 	        end                                          
    158. 	      else if (tx_en)
    159. 	        begin                                        
    160. 	          stream_data_out <= read_pointer + 32'b1;   //定义数据为指针+1
    161. 	        end                                          
    162. 	    end     
    163.  
    164. 	/* 
    165. 		实现用户逻辑
    166. 	*/
    167.  
    168. 	endmodule

    1.2 源码展示

    1. `timescale 1 ns / 1 ps
    2.  
    3. 	module axis_m_v1_0_M00_AXIS #
    4. 	(
    5. 		// Users to add parameters here
    6.  
    7. 		// User parameters ends
    8. 		// Do not modify the parameters beyond this line
    9.  
    10. 		// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
    11. 		parameter integer C_M_AXIS_TDATA_WIDTH	= 32,
    12. 		// Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
    13. 		parameter integer C_M_START_COUNT	= 32
    14. 	)
    15. 	(
    16. 		// Users to add ports here
    17.  
    18. 		// User ports ends
    19. 		// Do not modify the ports beyond this line
    20.  
    21. 		// Global ports
    22. 		input wire  M_AXIS_ACLK,
    23. 		// 
    24. 		input wire  M_AXIS_ARESETN,
    25. 		// Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. 
    26. 		output wire  M_AXIS_TVALID,
    27. 		// TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
    28. 		output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
    29. 		// TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
    30. 		output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
    31. 		// TLAST indicates the boundary of a packet.
    32. 		output wire  M_AXIS_TLAST,
    33. 		// TREADY indicates that the slave can accept a transfer in the current cycle.
    34. 		input wire  M_AXIS_TREADY
    35. 	);
    36. 	// Total number of output data                                                 
    37. 	localparam NUMBER_OF_OUTPUT_WORDS = 8;                                               
    38. 	                                                                                     
    39. 	// function called clogb2 that returns an integer which has the                      
    40. 	// value of the ceiling of the log base 2.                                           
    41. 	function integer clogb2 (input integer bit_depth);                                   
    42. 	  begin                                                                              
    43. 	    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)                                      
    44. 	      bit_depth = bit_depth >> 1;                                                    
    45. 	  end                                                                                
    46. 	endfunction                                                                          
    47. 	                                                                                     
    48. 	// WAIT_COUNT_BITS is the width of the wait counter.                                 
    49. 	localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);                      
    50. 	                                                                                     
    51. 	// bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.  
    52. 	localparam bit_num  = clogb2(NUMBER_OF_OUTPUT_WORDS);                                
    53. 	                                                                                     
    54. 	// Define the states of state machine                                                
    55. 	// The control state machine oversees the writing of input streaming data to the FIFO,
    56. 	// and outputs the streaming data from the FIFO                                      
    57. 	parameter [1:0] IDLE = 2'b00,        // This is the initial/idle state               
    58. 	                                                                                     
    59. 	                INIT_COUNTER  = 2'b01, // This state initializes the counter, once   
    60. 	                                // the counter reaches C_M_START_COUNT count,        
    61. 	                                // the state machine changes state to SEND_STREAM     
    62. 	                SEND_STREAM   = 2'b10; // In this state the                          
    63. 	                                     // stream data is output through M_AXIS_TDATA   
    64. 	// State variable                                                                    
    65. 	reg [1:0] mst_exec_state;                                                            
    66. 	// Example design FIFO read pointer                                                  
    67. 	reg [bit_num-1:0] read_pointer;                                                      
    69. 	// AXI Stream internal signals
    70. 	//wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
    71. 	reg [WAIT_COUNT_BITS-1 : 0] 	count;
    72. 	//streaming data valid
    73. 	wire  	axis_tvalid;
    74. 	//streaming data valid delayed by one clock cycle
    75. 	reg  	axis_tvalid_delay;
    76. 	//Last of the streaming data 
    77. 	wire  	axis_tlast;
    78. 	//Last of the streaming data delayed by one clock cycle
    79. 	reg  	axis_tlast_delay;
    80. 	//FIFO implementation signals
    81. 	reg [C_M_AXIS_TDATA_WIDTH-1 : 0] 	stream_data_out;
    82. 	wire  	tx_en;
    83. 	//The master has issued all the streaming data stored in FIFO
    84. 	reg  	tx_done;
    87. 	// I/O Connections assignments
    89. 	assign M_AXIS_TVALID	= axis_tvalid_delay;
    90. 	assign M_AXIS_TDATA	= stream_data_out;
    91. 	assign M_AXIS_TLAST	= axis_tlast_delay;
    92. 	assign M_AXIS_TSTRB	= {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
    93.  
    94.  
    95. 	// Control state machine implementation                             
    96. 	always @(posedge M_AXIS_ACLK)                                             
    97. 	begin                                                                     
    98. 	  if (!M_AXIS_ARESETN)                                                    
    99. 	  // Synchronous reset (active low)                                       
    100. 	    begin                                                                 
    101. 	      mst_exec_state <= IDLE;                                             
    102. 	      count    <= 0;                                                      
    103. 	    end                                                                   
    104. 	  else                                                                    
    105. 	    case (mst_exec_state)                                                 
    106. 	      IDLE:                                                               
    107. 	        // The slave starts accepting tdata when                          
    108. 	        // there tvalid is asserted to mark the                           
    109. 	        // presence of valid streaming data                               
    110. 	        //if ( count == 0 )                                                 
    111. 	        //  begin                                                           
    112. 	            mst_exec_state  <= INIT_COUNTER;                              
    113. 	        //  end                                                             
    114. 	        //else                                                              
    115. 	        //  begin                                                           
    116. 	        //    mst_exec_state  <= IDLE;                                      
    117. 	        //  end                                                             
    118. 	                                                                          
    119. 	      INIT_COUNTER:                                                       
    120. 	        // The slave starts accepting tdata when                          
    121. 	        // there tvalid is asserted to mark the                           
    122. 	        // presence of valid streaming data                               
    123. 	        if ( count == C_M_START_COUNT - 1 )                               
    124. 	          begin                                                           
    125. 	            mst_exec_state  <= SEND_STREAM;                               
    126. 	          end                                                             
    127. 	        else                                                              
    128. 	          begin                                                           
    129. 	            count <= count + 1;                                           
    130. 	            mst_exec_state  <= INIT_COUNTER;                              
    131. 	          end                                                             
    132. 	                                                                          
    133. 	      SEND_STREAM:                                                        
    134. 	        // The example design streaming master functionality starts       
    135. 	        // when the master drives output tdata from the FIFO and the slave
    136. 	        // has finished storing the S_AXIS_TDATA                          
    137. 	        if (tx_done)                                                      
    138. 	          begin                                                           
    139. 	            mst_exec_state <= IDLE;                                       
    140. 	          end                                                             
    141. 	        else                                                              
    142. 	          begin                                                           
    143. 	            mst_exec_state <= SEND_STREAM;                                
    144. 	          end                                                             
    145. 	    endcase                                                               
    146. 	end                                                                       
    147.  
    148.  
    149. 	//tvalid generation
    150. 	//axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
    151. 	//number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
    152. 	assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
    153. 	                                                                                               
    154. 	// AXI tlast generation                                                                        
    155. 	// axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1          
    156. 	// (0 to NUMBER_OF_OUTPUT_WORDS-1)                                                             
    157. 	assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);                                
    158. 	                                                                                               
    159. 	                                                                                               
    160. 	// Delay the axis_tvalid and axis_tlast signal by one clock cycle                              
    161. 	// to match the latency of M_AXIS_TDATA                                                        
    162. 	always @(posedge M_AXIS_ACLK)                                                                  
    163. 	begin                                                                                          
    164. 	  if (!M_AXIS_ARESETN)                                                                         
    165. 	    begin                                                                                      
    166. 	      axis_tvalid_delay <= 1'b0;                                                               
    167. 	      axis_tlast_delay <= 1'b0;                                                                
    168. 	    end                                                                                        
    169. 	  else                                                                                         
    170. 	    begin                                                                                      
    171. 	      axis_tvalid_delay <= axis_tvalid;                                                        
    172. 	      axis_tlast_delay <= axis_tlast;                                                          
    173. 	    end                                                                                        
    174. 	end                                                                                            
    177. 	//read_pointer pointer
    179. 	always@(posedge M_AXIS_ACLK)                                               
    180. 	begin                                                                            
    181. 	  if(!M_AXIS_ARESETN)                                                            
    182. 	    begin                                                                        
    183. 	      read_pointer <= 0;                                                         
    184. 	      tx_done <= 1'b0;                                                           
    185. 	    end                                                                          
    186. 	  else                                                                           
    187. 	    if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)                                
    188. 	      begin                                                                      
    189. 	        if (tx_en)                                                               
    190. 	          // read pointer is incremented after every read from the FIFO          
    191. 	          // when FIFO read signal is enabled.                                   
    192. 	          begin                                                                  
    193. 	            read_pointer <= read_pointer + 1;                                    
    194. 	            tx_done <= 1'b0;                                                     
    195. 	          end                                                                    
    196. 	      end                                                                        
    197. 	    else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)                             
    198. 	      begin                                                                      
    199. 	        // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
    200. 	        // has been out.                                                         
    201. 	        tx_done <= 1'b1;                                                         
    202. 	      end                                                                        
    203. 	end                                                                              
    204.  
    205.  
    206. 	//FIFO read enable generation 
    207.  
    208. 	assign tx_en = M_AXIS_TREADY && axis_tvalid;   
    209. 	                                                     
    210. 	    // Streaming output data is read from FIFO       
    211. 	    always @( posedge M_AXIS_ACLK )                  
    212. 	    begin                                            
    213. 	      if(!M_AXIS_ARESETN)                            
    214. 	        begin                                        
    215. 	          stream_data_out <= 1;                      
    216. 	        end                                          
    217. 	      else if (tx_en)// && M_AXIS_TSTRB[byte_index]  
    218. 	        begin                                        
    219. 	          stream_data_out <= read_pointer + 32'b1;   
    220. 	        end                                          
    221. 	    end                                              
    223. 	// Add user logic here
    225. 	// User logic ends
    227. 	endmodule

    2、AXIS从机部分

    1.1 中文注释

    1.  
    2. `timescale 1 ns / 1 ps
    3.  
    4. 	module axis_s_v1_0_S00_AXIS #
    5. 	(
    6. 		/*
    7. 			用户可以自定义参数
    8. 		*/
    9.  
    10. 		//AXIS数据位宽
    11. 		parameter integer C_S_AXIS_TDATA_WIDTH	= 32
    12. 	)
    13. 	(
    14. 		/*
    15. 			用户可以在此自定义端口
    16. 		*/
    17.  
    18. 		input wire  S_AXIS_ACLK,                    			  //时钟信号
    19. 		input wire  S_AXIS_ARESETN,               			      //复位信号
    20. 		output wire  S_AXIS_TREADY,              			      //ready信号，代表从机准备好了
    21. 		input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,     //数据信号
    22. 		input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB, //数据修饰符，辨别字节类型	
    23. 		input wire  S_AXIS_TLAST,								  //last信号，拉高代表是传输中的最后一个字节
    24. 		input wire  S_AXIS_TVALID                                 //ready信号，代表从机准备好了
    25. 	);
    26.  
    27. 	//函数：以2为低求对数，用于计算位宽
    28. 	function integer clogb2 (input integer bit_depth);
    29. 	  begin
    30. 	    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
    31. 	      bit_depth = bit_depth >> 1;
    32. 	  end
    33. 	endfunction
    34.  
    35. 	localparam NUMBER_OF_INPUT_WORDS  = 8;                      //输入数据个数
    36. 	localparam bit_num  = clogb2(NUMBER_OF_INPUT_WORDS-1);      //输入数据的位宽
    37.  
    38. 	//状态机定义
    39. 	parameter [1:0] IDLE = 1'b0,                                //初始状态
    40. 	                WRITE_FIFO  = 1'b1;                         //读状态
    41.  
    42. 	wire  	axis_tready;                                        //ready信号
    43.  
    44. 	reg mst_exec_state;                                         //状态寄存器
    45.  
    46. 	genvar byte_index;                                          //字节索引
    47.  
    48. 	wire fifo_wren;                                             //FIFO写使能
    49. 	reg fifo_full_flag;                                         //FIFO满标志
    50. 	reg [bit_num-1:0] write_pointer;                            //FIFO写指针
    51. 	reg writes_done;                                            //写满标志
    52.  
    53. 	assign S_AXIS_TREADY	= axis_tready;                    
    54.  
    55. 	//状态机
    56. 	always @(posedge S_AXIS_ACLK) 
    57. 	begin  
    58. 	  if (!S_AXIS_ARESETN) 
    59. 	    begin
    60. 	      mst_exec_state <= IDLE;
    61. 	    end  
    62. 	  else
    63. 	    case (mst_exec_state)
    64. 	      IDLE: 
    65. 	          if (S_AXIS_TVALID)
    66. 	            begin
    67. 	              mst_exec_state <= WRITE_FIFO;
    68. 	            end
    69. 	          else
    70. 	            begin
    71. 	              mst_exec_state <= IDLE;
    72. 	            end
    73. 	      WRITE_FIFO: 
    74. 	        if (writes_done)
    75. 	          begin
    76. 	            mst_exec_state <= IDLE;
    77. 	          end
    78. 	        else
    79. 	          begin
    80. 	            mst_exec_state <= WRITE_FIFO;
    81. 	          end
    82.  
    83. 	    endcase
    84. 	end
    85.  
    86. 	//ready信号赋值，写状态+读指针写于等于接收数据总个数
    87. 	assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
    88.  
    89. 	//写指针，写完成信号
    90. 	always@(posedge S_AXIS_ACLK)
    91. 	begin
    92. 	  if(!S_AXIS_ARESETN)
    93. 	    begin
    94. 	      write_pointer <= 0;
    95. 	      writes_done <= 1'b0;
    96. 	    end  
    97. 	  else
    98. 	    if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
    99. 	      begin
    100. 	        if (fifo_wren)
    101. 	          begin
    102. 	            write_pointer <= write_pointer + 1;
    103. 	            writes_done <= 1'b0;
    104. 	          end
    105. 	          if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
    106. 	            begin
    107. 	              writes_done <= 1'b1;
    108. 	            end
    109. 	      end  
    110. 	end
    112. 	//FIFO写使能信号
    113. 	assign fifo_wren = S_AXIS_TVALID && axis_tready;
    115. 	//例化4个宽为8，深度为8的二维数组stream_data_fifo，用来充当FIFO，每个FIFO依次写入数据的0-7；8-15；16-23；24-31位
    116. 	generate 
    117. 	  for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
    118. 	  begin:FIFO_GEN
    120. 	    reg  [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
    122. 		//写入FIFO数据
    123. 	    always @( posedge S_AXIS_ACLK )
    124. 	    begin
    125. 	      if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
    126. 	        begin
    127. 	          stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
    128. 	        end  
    129. 	    end  
    130. 	  end		
    131. 	endgenerate
    133. 	/* 
    134. 		实现用户逻辑
    135. 	*/
    137. 	endmodule

    1.2 源码展示

    1.  
    2. `timescale 1 ns / 1 ps
    3.  
    4. 	module axis_s_v1_0_S00_AXIS #
    5. 	(
    6. 		// Users to add parameters here
    7.  
    8. 		// User parameters ends
    9. 		// Do not modify the parameters beyond this line
    10.  
    11. 		// AXI4Stream sink: Data Width
    12. 		parameter integer C_S_AXIS_TDATA_WIDTH	= 32
    13. 	)
    14. 	(
    15. 		// Users to add ports here
    16.  
    17. 		// User ports ends
    18. 		// Do not modify the ports beyond this line
    19.  
    20. 		// AXI4Stream sink: Clock
    21. 		input wire  S_AXIS_ACLK,
    22. 		// AXI4Stream sink: Reset
    23. 		input wire  S_AXIS_ARESETN,
    24. 		// Ready to accept data in
    25. 		output wire  S_AXIS_TREADY,
    26. 		// Data in
    27. 		input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
    28. 		// Byte qualifier
    29. 		input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
    30. 		// Indicates boundary of last packet
    31. 		input wire  S_AXIS_TLAST,
    32. 		// Data is in valid
    33. 		input wire  S_AXIS_TVALID
    34. 	);
    35. 	// function called clogb2 that returns an integer which has the 
    36. 	// value of the ceiling of the log base 2.
    37. 	function integer clogb2 (input integer bit_depth);
    38. 	  begin
    39. 	    for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
    40. 	      bit_depth = bit_depth >> 1;
    41. 	  end
    42. 	endfunction
    43.  
    44. 	// Total number of input data.
    45. 	localparam NUMBER_OF_INPUT_WORDS  = 8;
    46. 	// bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
    47. 	localparam bit_num  = clogb2(NUMBER_OF_INPUT_WORDS-1);
    48. 	// Define the states of state machine
    49. 	// The control state machine oversees the writing of input streaming data to the FIFO,
    50. 	// and outputs the streaming data from the FIFO
    51. 	parameter [1:0] IDLE = 1'b0,        // This is the initial/idle state 
    53. 	                WRITE_FIFO  = 1'b1; // In this state FIFO is written with the
    54. 	                                    // input stream data S_AXIS_TDATA 
    55. 	wire  	axis_tready;
    56. 	// State variable
    57. 	reg mst_exec_state;  
    58. 	// FIFO implementation signals
    59. 	genvar byte_index;     
    60. 	// FIFO write enable
    61. 	wire fifo_wren;
    62. 	// FIFO full flag
    63. 	reg fifo_full_flag;
    64. 	// FIFO write pointer
    65. 	reg [bit_num-1:0] write_pointer;
    66. 	// sink has accepted all the streaming data and stored in FIFO
    67. 	  reg writes_done;
    68. 	// I/O Connections assignments
    69.  
    70. 	assign S_AXIS_TREADY	= axis_tready;
    71. 	// Control state machine implementation
    72. 	always @(posedge S_AXIS_ACLK) 
    73. 	begin  
    74. 	  if (!S_AXIS_ARESETN) 
    75. 	  // Synchronous reset (active low)
    76. 	    begin
    77. 	      mst_exec_state <= IDLE;
    78. 	    end  
    79. 	  else
    80. 	    case (mst_exec_state)
    81. 	      IDLE: 
    82. 	        // The sink starts accepting tdata when 
    83. 	        // there tvalid is asserted to mark the
    84. 	        // presence of valid streaming data 
    85. 	          if (S_AXIS_TVALID)
    86. 	            begin
    87. 	              mst_exec_state <= WRITE_FIFO;
    88. 	            end
    89. 	          else
    90. 	            begin
    91. 	              mst_exec_state <= IDLE;
    92. 	            end
    93. 	      WRITE_FIFO: 
    94. 	        // When the sink has accepted all the streaming input data,
    95. 	        // the interface swiches functionality to a streaming master
    96. 	        if (writes_done)
    97. 	          begin
    98. 	            mst_exec_state <= IDLE;
    99. 	          end
    100. 	        else
    101. 	          begin
    102. 	            // The sink accepts and stores tdata 
    103. 	            // into FIFO
    104. 	            mst_exec_state <= WRITE_FIFO;
    105. 	          end
    106.  
    107. 	    endcase
    108. 	end
    109. 	// AXI Streaming Sink 
    110. 	// 
    111. 	// The example design sink is always ready to accept the S_AXIS_TDATA  until
    112. 	// the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
    113. 	assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
    114.  
    115. 	always@(posedge S_AXIS_ACLK)
    116. 	begin
    117. 	  if(!S_AXIS_ARESETN)
    118. 	    begin
    119. 	      write_pointer <= 0;
    120. 	      writes_done <= 1'b0;
    121. 	    end  
    122. 	  else
    123. 	    if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
    124. 	      begin
    125. 	        if (fifo_wren)
    126. 	          begin
    127. 	            // write pointer is incremented after every write to the FIFO
    128. 	            // when FIFO write signal is enabled.
    129. 	            write_pointer <= write_pointer + 1;
    130. 	            writes_done <= 1'b0;
    131. 	          end
    132. 	          if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
    133. 	            begin
    134. 	              // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data 
    135. 	              // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
    136. 	              writes_done <= 1'b1;
    137. 	            end
    138. 	      end  
    139. 	end
    141. 	// FIFO write enable generation
    142. 	assign fifo_wren = S_AXIS_TVALID && axis_tready;
    144. 	// FIFO Implementation
    145. 	generate 
    146. 	  for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
    147. 	  begin:FIFO_GEN
    149. 	    reg  [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
    151. 	    // Streaming input data is stored in FIFO
    153. 	    always @( posedge S_AXIS_ACLK )
    154. 	    begin
    155. 	      if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
    156. 	        begin
    157. 	          stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
    158. 	        end  
    159. 	    end  
    160. 	  end		
    161. 	endgenerate
    163. 	// Add user logic here
    165. 	// User logic ends
    167. 	endmodule

    四、仿真测试

    1、top

    1. module top(
    2.     input clk,
    3.     input rst_n
    4.     );
    5.  
    6.     wire [31:0] axis_tdata;
    7.     wire [3:0]  axis_tstrb;
    8.     wire        axis_tlast;
    9.     wire        axis_tready;
    10.     wire        axis_tvalid;
    11.  
    12.     axis_m_0 axis_m_u0
    13.     (
    14.      .m00_axis_tdata      (axis_tdata),
    15.      .m00_axis_tstrb      (axis_tstrb), 
    16.      .m00_axis_tlast      (axis_tlast),
    17.      .m00_axis_tvalid     (axis_tvalid),
    18.      .m00_axis_tready     (axis_tready),
    19.      .m00_axis_aclk       (clk),
    20.      .m00_axis_aresetn    (rst_n)
    21.     );
    22.  
    23.     axis_s_0 axis_s_u0
    24.     (
    25.      .s00_axis_tdata      (axis_tdata),
    26.      .s00_axis_tstrb      (axis_tstrb), 
    27.      .s00_axis_tlast      (axis_tlast),
    28.      .s00_axis_tvalid     (axis_tvalid),
    29.      .s00_axis_tready     (axis_tready),
    30.      .s00_axis_aclk       (clk),
    31.      .s00_axis_aresetn    (rst_n)
    32.     );
    33.  
    34. endmodule

    2、tb

    1. `timescale 1ns / 1ps
    2.  
    3. module tb_top();
    4.     reg clk,rst_n;
    5.  
    6. initial begin
    7.     clk = 0;
    8.     rst_n = 1;
    9. #10
    10.     rst_n = 0;
    11. #10
    12.     rst_n = 1;
    13. end
    14.  
    15. always #5 clk <= ~clk;
    16.  
    17. top top_u1(.clk(clk),
    18.            .rst_n(rst_n));
    19.  
    20. endmodule

    3、结果

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  • 原文地址：https://blog.csdn.net/apple_53311083/article/details/134071768