[HDLBits] Exams/2014 q3fsm

Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.

Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.

AAB...

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
	parameter a=0,b0=1,b1=2,b2=3;
    reg [1:0] state,next,count;
    //状态机只是帮助我们解决问题的一个工具，这里用状态机+count一起解决问题
    always@(*) begin
        case(state)
            a:next<=s?b0:a;
            b0:next<=b1;
            b1:next<=b2;
            b2:next<=b0;
        endcase
    end
    always@(posedge clk) begin
        if(reset) begin
            count<=0;
            state<=a;
        end
        else begin
            if(state==a)
                count<=0;
            else if(state==b0)
                count<=w;
            else
                count<=count+w;
            state<=next;
        end
    end
    assign z=(count==2&&state==b0);
    //这里需要加上state为b0的设置，否则可能在11时就输出z=1了
endmodule