• BL808学习日志-2-LVGL for M0 and D0

    一、lvgl测试环境

            对拿到的M1S_DOCK开发板进行开发板测试，博流的官方SDK是支持M0和D0两个内核都进行测试的；但是目前只实现了M0的LVGLBenchmark，测试D0内核中发现很多莫名其妙的问题。一会详细记录。

            使用的是开发板自带的SPI显示屏，280*240分辨率。

    二、M0内核lvgl测试

            使用官方默认的SDK进行编译会报错缓存不够，按照下列方式修改SDK中的.ld内存分布文件

    /bouffalo_sdk/bsp/board/bl808dk/bl808_flash_m0.ld文件。主要目的就是修改ram_memory的大小，把ram_wifi的大小暂时调整为0，因为目前官方SDK无法启用无线功能。如果测试过程中卡住，就是ram_memory太小了，缓存不够使用了，调大即可。

    1. /****************************************************************************************
    2. * @file flash.ld
    3. *
    4. * @brief This file is the link script file (gnuarm or armgcc).
    5. *
    6. * Copyright (C) BouffaloLab 2021
    7. *
    8. ****************************************************************************************
    9. */
    10.  
    11. /* configure the CPU type */
    12. OUTPUT_ARCH( "riscv" )
    13.  
    14. /* configure the entry point */
    15. ENTRY(__start)
    16.  
    17. StackSize    = 0x0400; /*  1KB */
    18. HeapMinSize  = 0x1000; /*  4KB */
    19. psram_min_size = 0x1000;
    20.  
    21. __EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K;
    22.  
    23. MEMORY
    24. {
    25.     fw_header_memory  (rx)  : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
    26.     xip_memory  (rx)  : ORIGIN = 0x58000000, LENGTH = 32M
    27.     ram_psram  (wxa)  : ORIGIN = 0x50000000, LENGTH = 64M
    28.     itcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 32K
    29.     dtcm_memory (rx)  : ORIGIN = 0x62028000, LENGTH = 16K
    30.     nocache_ram_memory (!rx) : ORIGIN = 0x2202C000, LENGTH = 16K
    31.     ram_memory  (!rx) : ORIGIN = 0x62038000, LENGTH = 128K
    32.     ram_wifi  (wxa)   : ORIGIN = 0x22058000, LENGTH = 0K
    33.     xram_memory  (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
    34. }
    35.  
    36. SECTIONS
    37. {
    38.     .fw_header :
    39.     {
    40.         KEEP(*(.fw_header))
    41.     } > fw_header_memory
    42.  
    43.     .init :
    44.     {
    45.         KEEP (*(SORT_NONE(.init)))
    46.         KEEP (*(SORT_NONE(.vector)))
    47.  
    48.     } > xip_memory
    49.  
    50.     .text :
    51.     {
    52.         . = ALIGN(4);
    53.         __text_code_start__ = .;
    54.  
    55.         *(.text)
    56.         *(.text.*)
    57.  
    58.         /* section information for shell */
    59.         . = ALIGN(4);
    60.         __fsymtab_start = .;
    61.         KEEP(*(FSymTab))
    62.         __fsymtab_end = .;
    63.  
    64.         . = ALIGN(4);
    65.         __vsymtab_start = .;
    66.         KEEP(*(VSymTab))
    67.         __vsymtab_end = .;
    68.  
    69.         /* section information for usb usbh_class_info */
    70.         . = ALIGN(4);
    71.         __usbh_class_info_start__ = .;
    72.         KEEP(*(.usbh_class_info))
    73.         . = ALIGN(4);
    74.         __usbh_class_info_end__ = .;
    75.  
    76.         /*put .rodata**/
    77.         *(EXCLUDE_FILE( *bl808_glb*.o* \
    78.                         *bl808_glb_gpio*.o* \
    79.                         *bl808_pds*.o* \
    80.                         *bl808_aon*.o* \
    81.                         *bl808_hbn*.o* \
    82.                         *bl808_l1c*.o* \
    83.                         *bl808_common*.o* \
    84.                         *bl808_clock*.o* \
    85.                         *bl808_ef_ctrl*.o* \
    86.                         *bl808_sf_cfg*.o* \
    87.                         *bl808_sf_ctrl*.o* \
    88.                         *bl808_sflash*.o* \
    89.                         *bl808_xip_sflash*.o* \
    90.                         *bl808_romapi_patch*.o* ) .rodata*)
    91.         *(.srodata)
    92.         *(.srodata.*)
    93.  
    94.         . = ALIGN(4);
    95.         __text_code_end__ = .;
    96.     } > xip_memory
    97.  
    98.     . = ALIGN(4);
    99.     __itcm_load_addr = .;
    100.  
    101.     .itcm_region : AT (__itcm_load_addr)
    102.     {
    103.         . = ALIGN(4);
    104.         __tcm_code_start__ = .;
    105.  
    106.         *(.tcm_code.*)
    107.         *(.tcm_const.*)
    108.         *(.sclock_rlt_code.*)
    109.         *(.sclock_rlt_const.*)
    110.  
    111.         *bl808_glb*.o*(.rodata*)
    112.         *bl808_glb_gpio*.o*(.rodata*)
    113.         *bl808_pds*.o*(.rodata*)
    114.         *bl808_aon*.o*(.rodata*)
    115.         *bl808_hbn*.o*(.rodata*)
    116.         *bl808_l1c*.o*(.rodata*)
    117.         *bl808_common*.o*(.rodata*)
    118.         *bl808_clock*.o*(.rodata*)
    119.         *bl808_ef_ctrl*.o*(.rodata*)
    120.         *bl808_sf_cfg*.o*(.rodata*)
    121.         *bl808_sf_ctrl*.o*(.rodata*)
    122.         *bl808_sflash*.o*(.rodata*)
    123.         *bl808_xip_sflash*.o*(.rodata*)
    124.         *bl808_romapi_patch*.o*(.rodata*)
    125.  
    126.         . = ALIGN(4);
    127.         __tcm_code_end__ = .;
    128.     } > itcm_memory
    129.  
    130.     __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
    131.  
    132.     .dtcm_region : AT (__dtcm_load_addr)
    133.     {
    134.         . = ALIGN(4);
    135.         __tcm_data_start__ = .;
    136.  
    137.         *(.tcm_data)
    138.         /* *finger_print.o(.data*) */
    139.  
    140.         . = ALIGN(4);
    141.         __tcm_data_end__ = .;
    142.     } > dtcm_memory
    143.  
    144.     /*************************************************************************/
    145.     /* .stack_dummy section doesn't contains any symbols. It is only
    146.      * used for linker to calculate size of stack sections, and assign
    147.      * values to stack symbols later */
    148.     .stack_dummy (NOLOAD):
    149.     {
    150.         . = ALIGN(0x4);
    151.         . = . + StackSize;
    152.         . = ALIGN(0x4);
    153.     } > dtcm_memory
    155.     /* Set stack top to end of RAM, and stack limit move down by
    156.      * size of stack_dummy section */
    157.     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
    158.     PROVIDE( __freertos_irq_stack_top = __StackTop);
    159.     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
    161.     /* Check if data + heap + stack exceeds RAM limit */
    162.     ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
    163.     /*************************************************************************/
    164.     __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
    166.     .nocache_ram_region  : AT (__nocache_ram_load_addr)
    167.     {
    168.         . = ALIGN(4);
    169.         __nocache_ram_data_start__ = .;
    171.         *(.nocache_ram)
    173.         . = ALIGN(4);
    174.         __nocache_ram_data_end__ = .;
    175.     } > nocache_ram_memory
    177.     __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
    179.     /* Data section */
    180.     RAM_DATA : AT (__ram_load_addr)
    181.     {
    182.         . = ALIGN(4);
    183.         __ram_data_start__ = .;
    185.         PROVIDE( __global_pointer$ = . + 0x800 );
    187.         *(.data)
    188.         *(.data.*)
    189.         *(.sdata)
    190.         *(.sdata.*)
    191.         *(.sdata2)
    192.         *(.sdata2.*)
    194.         . = ALIGN(4);
    195.         __bflog_tags_start__ = .;
    196.         *(.bflog_tags_array)
    197.         . = ALIGN(4);
    198.         __bflog_tags_end__ = .;
    199.         __ram_data_end__ = .;
    200.     } > ram_memory
    202.     __psram_load_addr = (__ram_load_addr + SIZEOF (RAM_DATA));
    204.     .psram_data_region : AT (__psram_load_addr)
    205.     {
    206.         . = ALIGN(4);
    207.         __psram_data_start__ = .;
    209.         KEEP(*(.psram_data*))
    211.         . = ALIGN(4);
    212.         __psram_data_end__ = .;
    213.     } > ram_psram
    215.     __etext_final = (__psram_load_addr + SIZEOF (.psram_data_region));
    216.     ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
    218.     .bss (NOLOAD) :
    219.     {
    220.         . = ALIGN(4);
    221.         __bss_start__ = .;
    223.         *(.bss*)
    224.         *(.sbss*)
    225.         *(COMMON)
    227.         . = ALIGN(4);
    228.         __bss_end__ = .;
    229.     } > ram_memory
    231.     .noinit_data (NOLOAD) :
    232.     {
    233.         . = ALIGN(4);
    234.         __noinit_data_start__ = .;
    236.         *(.noinit_data*)
    238.         . = ALIGN(4);
    239.         __noinit_data_end__ = .;
    240.     } > ram_memory
    242.     .nocache_noinit_ram_region (NOLOAD) :
    243.     {
    244.         . = ALIGN(4);
    245.         __nocache_noinit_ram_data_start__ = .;
    247.         *(.nocache_noinit_ram)
    248.         *(.noncacheable)
    250.         . = ALIGN(4);
    251.         __nocache_noinit_ram_data_end__ = .;
    252.     } > nocache_ram_memory
    254.     .heap (NOLOAD):
    255.     {
    256.         . = ALIGN(4);
    257.         __HeapBase = .;
    259.         /*__end__ = .;*/
    260.         /*end = __end__;*/
    261.         KEEP(*(.heap*))
    263.         . = ALIGN(4);
    264.         __HeapLimit = .;
    265.     } > ram_memory
    267.     __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
    268.     ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
    270.     .psram_noinit_data (NOLOAD):
    271.     {
    272.         . = ALIGN(4);
    273.         __psram_noinit_data_start__ = .;
    275.         KEEP(*(.psram_noinit*))
    277.         . = ALIGN(4);
    278.         __psram_noinit_data_end__ = .;
    279.     } > ram_psram
    281.     .psram_heap (NOLOAD):
    282.     {
    283.         . = ALIGN(4);
    284.         __psram_heap_base = .;
    285.         KEEP(*(.psram_heap*))
    286.         . = ALIGN(4);
    287.         __psram_heap_end = .;
    288.     } > ram_psram
    290.     __psram_limit = ORIGIN(ram_psram) + LENGTH(ram_psram);
    291.     ASSERT(__psram_limit - __psram_heap_base >= psram_min_size, "psram heap region overflow")
    292.  
    293.     .wifibss  (NOLOAD) :
    294.     {
    295.         PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
    296.         PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
    297.         *ipc_shared.o(COMMON)
    298.         *sdu_shared.o(COMMON)
    299.         *hal_desc.o(COMMON)
    300.         *txl_buffer_shared.o(COMMON)
    301.         *txl_frame_shared.o(COMMON)
    302.         *scan_shared.o(COMMON)
    303.         *scanu_shared.o(COMMON)
    304.         *mfp_bip.o(COMMON)
    305.         *me_mic.o(COMMON)
    306.         *bl_sta_mgmt_others.o(COMMON)
    307.         *bl_pmk_mgmt.o(COMMON)
    308.         *bl_pmk_mgmt_internal.o(COMMON)
    309.         *libwifi_drv.a:bl_utils.o(COMMON)
    310.         *libwifi_drv.a:bl_utils.o(.bss*)
    311.         *(.wifi_ram*)
    312.         . = ALIGN(16);
    313.     } > ram_wifi
    315.     PROVIDE(__LD_CONFIG_EM_SEL = __EM_SIZE);
    316. }

            修改完成后最好把LP内核的内存分布文件也修改一下。这里引申出一个问题，就是内存的分布肯定是LP和M0内核共享OCRAM+WRAM，但是不知道两个内核的itcm_memory 和dtcm_memory的大小是不是要按照规格书改成32K+16K，官方默认的大小是20K+4K，搞不懂是什么用意。而且两个内核的部分区域在官方SDK中竟然重叠了，好奇怪。对于初学者来说，实在是头大，官方也没有任何说明。

            这里直接贴图一个成绩。

    1.  
    2.   ____               __  __      _       _       _
    3.  |  _ \             / _|/ _|    | |     | |     | |
    4.  | |_) | ___  _   _| |_| |_ __ _| | ___ | | __ _| |__
    5.  |  _ < / _ \| | | |  _|  _/ _` | |/ _ \| |/ _` | '_ \
    6.  | |_) | (_) | |_| | | | || (_| | | (_) | | (_| | |_) |
    7.  |____/ \___/ \__,_|_| |_| \__,_|_|\___/|_|\__,_|_.__/
    8.  
    9. Build:10:29:32,Oct  4 2023
    10. Copyright (c) 2022 Bouffalolab team
    11. ======== flash cfg ========
    12. flash size 0x01000000
    13. jedec id     0xEF4018
    14. mid              0xEF
    15. iomode           0x04
    16. clk delay        0x01
    17. clk invert       0x01
    18. read reg cmd0    0x05
    19. read reg cmd1    0x35
    20. write reg cmd0   0x01
    21. write reg cmd1   0x31
    22. qe write len     0x01
    23. cread support    0x00
    24. cread code       0xFF
    25. burst wrap cmd   0x77
    26. ===========================
    27. dynamic memory init success,heap size = 86 Kbyte
    28. sig1:ffff32ff
    29. sig2:0000ffff
    30. lvgl case
    31. lvgl success
    32. [LVGL]
    33. LVGL v8.3.7  Benchmark (in csv format)
    34. [LVGL] Weighted FPS: 67
    35. [LVGL] Opa. speed: 97%
    36. [LVGL] Text small,19
    37. [LVGL] Text small + opa,[LVGL] 19
    38. [LVGL] Text medium,19
    39. [LVGL] Text medium + opa,[LVGL] 19
    40. [LVGL] Text large,19
    41. [LVGL] Text large + opa,[LVGL] 19
    42. [LVGL] Text large compressed,16
    43. [LVGL] Substr. shadow,19
    44. [LVGL] Substr. text,15
    45. [LVGL] Rectangle,60
    46. [LVGL] Rectangle + opa,[LVGL] 57
    47. [LVGL] Rectangle rounded,53
    48. [LVGL] Rectangle rounded + opa,[LVGL] 52
    49. [LVGL] Circle,49
    50. [LVGL] Circle + opa,[LVGL] 48
    51. [LVGL] Border,59
    52. [LVGL] Border + opa,[LVGL] 59
    53. [LVGL] Border rounded,52
    54. [LVGL] Border rounded + opa,[LVGL] 52
    55. [LVGL] Circle border,46
    56. [LVGL] Circle border + opa,[LVGL] 46
    57. [LVGL] Border top,54
    58. [LVGL] Border top + opa,[LVGL] 54
    59. [LVGL] Border left,54
    60. [LVGL] Border left + opa,[LVGL] 54
    61. [LVGL] Border top + left,53
    62. [LVGL] Border top + left + opa,[LVGL] 52
    63. [LVGL] Border left + right,53
    64. [LVGL] Border left + right + opa,[LVGL] 52
    65. [LVGL] Border top + bottom,52
    66. [LVGL] Border top + bottom + opa,[LVGL] 53
    67. [LVGL] Shadow small,40
    68. [LVGL] Shadow small + opa,[LVGL] 39
    69. [LVGL] Shadow small offset,35
    70. [LVGL] Shadow small offset + opa,[LVGL] 35
    71. [LVGL] Shadow large,26
    72. [LVGL] Shadow large + opa,[LVGL] 25
    73. [LVGL] Shadow large offset,27
    74. [LVGL] Shadow large offset + opa,[LVGL] 28
    75. [LVGL] Image RGB,170
    76. [LVGL] Image RGB + opa,[LVGL] 180
    77. [LVGL] Image ARGB,161
    78. [LVGL] Image ARGB + opa,[LVGL] 154
    79. [LVGL] Image chorma keyed,165
    80. [LVGL] Image chorma keyed + opa,[LVGL] 164
    81. [LVGL] Image indexed,150
    82. [LVGL] Image indexed + opa,[LVGL] 151
    83. [LVGL] Image alpha only,158
    84. [LVGL] Image alpha only + opa,[LVGL] 150
    85. [LVGL] Image RGB recolor,156
    86. [LVGL] Image RGB recolor + opa,[LVGL] 150
    87. [LVGL] Image ARGB recolor,142
    88. [LVGL] Image ARGB recolor + opa,[LVGL] 141
    89. [LVGL] Image chorma keyed recolor,151
    90. [LVGL] Image chorma keyed recolor + opa,[LVGL] 142
    91. [LVGL] Image indexed recolor,144
    92. [LVGL] Image indexed recolor + opa,[LVGL] 143
    93. [LVGL] Image RGB rotate,118
    94. [LVGL] Image RGB rotate + opa,[LVGL] 118
    95. [LVGL] Image RGB rotate anti aliased,100
    96. [LVGL] Image RGB rotate anti aliased + opa,[LVGL] 96
    97. [LVGL] Image ARGB rotate,114
    98. [LVGL] Image ARGB rotate + opa,[LVGL] 112
    99. [LVGL] Image ARGB rotate anti aliased,86
    100. [LVGL] Image ARGB rotate anti aliased + opa,[LVGL] 86
    101. [LVGL] Image RGB zoom,125
    102. [LVGL] Image RGB zoom + opa,[LVGL] 121
    103. [LVGL] Image RGB zoom anti aliased,108
    104. [LVGL] Image RGB zoom anti aliased + opa,[LVGL] 107
    105. [LVGL] Image ARGB zoom,118
    106. [LVGL] Image ARGB zoom + opa,[LVGL] 120
    107. [LVGL] Image ARGB zoom anti aliased,97
    108. [LVGL] Image ARGB zoom anti aliased + opa,[LVGL] 98
    109. [LVGL] Text small,19
    110. [LVGL] Text small + opa,[LVGL] 19
    111. [LVGL] Text medium,19
    112. [LVGL] Text medium + opa,[LVGL] 19
    113. [LVGL] Text large,19
    114. [LVGL] Text large + opa,[LVGL] 19
    115. [LVGL] Text small compressed,18
    116. [LVGL] Text small compressed + opa,[LVGL] 18
    117. [LVGL] Text medium compressed,17
    118. [LVGL] Text medium compressed + opa,[LVGL] 17
    119. [LVGL] Text large compressed,16
    120. [LVGL] Text large compressed + opa,[LVGL] 16
    121. [LVGL] Line,53
    122. [LVGL] Line + opa,[LVGL] 54
    123. [LVGL] Arc think,44
    124. [LVGL] Arc think + opa,[LVGL] 43
    125. [LVGL] Arc thick,44
    126. [LVGL] Arc thick + opa,[LVGL] 43
    127. [LVGL] Substr. rectangle,36
    128. [LVGL] Substr. rectangle + opa,[LVGL] 36
    129. [LVGL] Substr. border,37
    130. [LVGL] Substr. border + opa,[LVGL] 37
    131. [LVGL] Substr. shadow,19
    132. [LVGL] Substr. shadow + opa,[LVGL] 19
    133. [LVGL] Substr. image,125
    134. [LVGL] Substr. image + opa,[LVGL] 126
    135. [LVGL] Substr. line,33
    136. [LVGL] Substr. line + opa,[LVGL] 33
    137. [LVGL] Substr. arc,42
    138. [LVGL] Substr. arc + opa,[LVGL] 42
    139. [LVGL] Substr. text,15
    140. [LVGL] Substr. text + opa,[LVGL] 15

    三、D0内核调试挖坑！！！

            测试D0内核花费了3天时间也没搞定，总是进入初始化以后，直接就卡屏卡死了。因为在假期，没带DEBUG工具，只能随便打点测试了一下；

            1.SPI1无法启用

    按照官方SDK进行测试，发现根本没有使用SPI1，而且在lcd_spi_hard_4_init(lcd_spi_hard_4_init_t *dbi_parra)初始化过程中，spi_hd = bflb_device_get_by_name(LCD_SPI_HARD_4_NAME);得到的是spi0。。。

    1. int lcd_spi_hard_4_init(lcd_spi_hard_4_init_t *dbi_parra)
    2. {
    3.     /* spi */
    4.     struct bflb_spi_config_s spi_cfg = {
    5.         .freq = dbi_parra->clock_freq,
    6.         .role = SPI_ROLE_MASTER,
    7.         .mode = SPI_MODE3,
    8.         .data_width = SPI_DATA_WIDTH_8BIT,
    9.         .bit_order = SPI_BIT_MSB,
    10.         .byte_order = SPI_BYTE_LSB,
    11.         .tx_fifo_threshold = 0,
    12.         .rx_fifo_threshold = 0,
    13.     };
    14.  
    15.     /* dma cfg */
    16.     struct bflb_dma_channel_config_s dma_spi_tx_cfg = {
    17.         .direction = DMA_MEMORY_TO_PERIPH,
    18.         .src_req = DMA_REQUEST_NONE,
    19.         .dst_req = DMA_REQUEST_SPI0_TX,
    20.         .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,
    21.         .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE,
    22.         .src_burst_count = DMA_BURST_INCR4,
    23.         .dst_burst_count = DMA_BURST_INCR4,
    24.         .src_width = DMA_DATA_WIDTH_16BIT,
    25.         .dst_width = DMA_DATA_WIDTH_16BIT,
    26.     };
    27.  
    28.     pixel_format = dbi_parra->pixel_format;
    29.  
    30. #if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
    31.     /* SPI support burst*4 */
    32.     spi_cfg.tx_fifo_threshold = (2 * 4 - 1);
    33.     spi_cfg.rx_fifo_threshold = (2 * 4 - 1);
    34.     spi_cfg.byte_order = SPI_BYTE_MSB;
    35. #elif
    36.     spi_cfg.tx_fifo_threshold = 4 - 1;
    37.     spi_cfg.rx_fifo_threshold = 4 - 1;
    38. #endif
    39.  
    40.     spi_hd = bflb_device_get_by_name(LCD_SPI_HARD_4_NAME);
    41.  
    42.     /* CS and DC pin init */
    43.     gpio = bflb_device_get_by_name("gpio");
    44.     bflb_gpio_init(gpio, LCD_SPI_HARD_4_PIN_CS, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
    45.     bflb_gpio_init(gpio, LCD_SPI_HARD_4_PIN_DC, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
    46.     LCD_SPI_HARD_4_CS_HIGH;
    47.     LCD_SPI_HARD_4_DC_HIGH;
    48.  
    49.     if (spi_hd->idx == 0) {
    50.         bflb_gpio_init(gpio, LCD_SPI_HARD_4_PIN_CLK, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
    51.         bflb_gpio_init(gpio, LCD_SPI_HARD_4_PIN_DAT, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
    52.     }
    53. #if defined(GPIO_FUNC_SPI1)
    54.     else if (spi_hd->idx == 1) {
    55.         bflb_gpio_init(gpio, LCD_SPI_HARD_4_PIN_CLK, GPIO_FUNC_SPI1 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
    56.         bflb_gpio_init(gpio, LCD_SPI_HARD_4_PIN_DAT, GPIO_FUNC_SPI1 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
    57.     }
    58.  
    59. #endif
    60.  
    61.     /* spi init */
    62.     bflb_spi_init(spi_hd, &spi_cfg);
    63.  
    64.     /* spi enabled continuous mode */
    65.     // bflb_spi_feature_control(spi_hd, SPI_CMD_SET_CS_INTERVAL, true);
    66.  
    67.     if (pixel_format == LCD_SPI_LCD_PIXEL_FORMAT_RGB565) {
    68.         dma_spi_tx_cfg.src_width = DMA_DATA_WIDTH_16BIT;
    69.         dma_spi_tx_cfg.dst_width = DMA_DATA_WIDTH_16BIT;
    70.     }
    71.  
    72.     if (spi_hd->idx == 0) {
    73.         dma_spi_tx_cfg.dst_req = DMA_REQUEST_SPI0_TX;
    74.         spi_tx_fifo_address = DMA_ADDR_SPI0_TDR;
    75.     }
    76. #if defined(DMA_REQUEST_SPI1_TX)
    77.     else if (spi_hd->idx == 1) {
    78.         dma_spi_tx_cfg.dst_req = DMA_REQUEST_SPI1_TX;
    79.         spi_tx_fifo_address = DMA_ADDR_SPI1_TDR;
    80.     }
    81. #endif
    82.  
    83.     /* dma init */
    84.     spi_dma_hd = bflb_device_get_by_name(LCD_SPI_HARD_4_DMA_NAME);
    85.     bflb_dma_channel_init(spi_dma_hd, &dma_spi_tx_cfg);
    86.  
    87.     /* dma int cfg */
    88.     bflb_dma_channel_irq_attach(spi_dma_hd, spi_dma_callback, NULL);
    89.  
    90.     return 0;
    91. }

    按照device_table.c文件中，竟然没有规定spi1..........，也没有规定DMA2的对应0-7个通道，但是却规定了DMA0的0-7个通道，官方datasheet中DMA0和DMA1只有一个通道。8个通道的寄存器基地址都是DMA0_BASE(  #define DMA0_BASE ((uint32_t)0x2000c000)),在else这个分支里面竟然中断号都是0XFF,真是被这SDK搞懵了。看这样子好像官方并不想让使用spi1来使用？？？？？这个问题等待后续解决。

    1. { .name = "spi0",
    2.       .reg_base = SPI0_BASE,
    3. #if defined(CPU_M0) || defined(CPU_LP)
    4.       .irq_num = BL808_IRQ_SPI0,
    5. #else
    6.       .irq_num = 0xff,
    7. #endif
    8.       .idx = 0,
    9.       .dev_type = BFLB_DEVICE_TYPE_SPI,
    10.       .user_data = NULL 
    11. },
    12.  
    13.  
    14. { .name = "dma0_ch0",
    15.       .reg_base = DMA0_BASE + 1 * DMA_CHANNEL_OFFSET,
    16. #if defined(CPU_M0) || defined(CPU_LP)
    17.       .irq_num = BL808_IRQ_DMA0_ALL,
    18. #else
    19.       .irq_num = 0xff,
    20. #endif
    21.       .idx = 0,
    22.       .sub_idx = 0,
    23.       .dev_type = BFLB_DEVICE_TYPE_DMA,
    24.       .user_data = NULL 
    25. },

            2.补充一个使用M1S_DOCK_SDK测试出的D0内核的数据，大概是M0内核的2-2.5倍性能，好像也符合coremark的分数。大概是DMA速度不同吧。

    1. [LVGL] 
    2. LVGL v8.3.1  Benchmark (in csv format)
    3. [LVGL] Weighted FPS: 146
    4. [LVGL] Opa. speed: 93%
    5. [LVGL] Rectangle,97
    6. [LVGL] Rectangle + opa,[LVGL] 95
    7. [LVGL] Rectangle rounded,96
    8. [LVGL] Rectangle rounded + opa,[LVGL] 91
    9. [LVGL] Circle,95
    10. [LVGL] Circle + opa,[LVGL] 85
    11. [LVGL] Border,101
    12. [LVGL] Border + opa,[LVGL] 99
    13. [LVGL] Border rounded,96
    14. [LVGL] Border rounded + opa,[LVGL] 95
    15. [LVGL] Circle border,90
    16. [LVGL] Circle border + opa,[LVGL] 90
    17. [LVGL] Border top,98
    18. [LVGL] Border top + opa,[LVGL] 97
    19. [LVGL] Border left,97
    20. [LVGL] Border left + opa,[LVGL] 98
    21. [LVGL] Border top + left,96
    22. [LVGL] Border top + left + opa,[LVGL] 96
    23. [LVGL] Border left + right,96
    24. [LVGL] Border left + right + opa,[LVGL] 95
    25. [LVGL] Border top + bottom,96
    26. [LVGL] Border top + bottom + opa,[LVGL] 96
    27. [LVGL] Shadow small,76
    28. [LVGL] Shadow small + opa,[LVGL] 76
    29. [LVGL] Shadow small offset,66
    30. [LVGL] Shadow small offset + opa,[LVGL] 65
    31. [LVGL] Shadow large,42
    32. [LVGL] Shadow large + opa,[LVGL] 43
    33. [LVGL] Shadow large offset,45
    34. [LVGL] Shadow large offset + opa,[LVGL] 44
    35. [LVGL] Image RGB,418
    36. [LVGL] Image RGB + opa,[LVGL] 388
    37. [LVGL] Image ARGB,418
    38. [LVGL] Image ARGB + opa,[LVGL] 390
    39. [LVGL] Image chorma keyed,415
    40. [LVGL] Image chorma keyed + opa,[LVGL] 388
    41. [LVGL] Image indexed,368
    42. [LVGL] Image indexed + opa,[LVGL] 333
    43. [LVGL] Image alpha only,362
    44. [LVGL] Image alpha only + opa,[LVGL] 328
    45. [LVGL] Image RGB recolor,382
    46. [LVGL] Image RGB recolor + opa,[LVGL] 318
    47. [LVGL] Image ARGB recolor,345
    48. [LVGL] Image ARGB recolor + opa,[LVGL] 322
    49. [LVGL] Image chorma keyed recolor,370
    50. [LVGL] Image chorma keyed recolor + opa,[LVGL] 331
    51. [LVGL] Image indexed recolor,320
    52. [LVGL] Image indexed recolor + opa,[LVGL] 288
    53. [LVGL] Image RGB rotate,264
    54. [LVGL] Image RGB rotate + opa,[LVGL] 225
    55. [LVGL] Image RGB rotate anti aliased,187
    56. [LVGL] Image RGB rotate anti aliased + opa,[LVGL] 170
    57. [LVGL] Image ARGB rotate,263
    58. [LVGL] Image ARGB rotate + opa,[LVGL] 226
    59. [LVGL] Image ARGB rotate anti aliased,178
    60. [LVGL] Image ARGB rotate anti aliased + opa,[LVGL] 167
    61. [LVGL] Image RGB zoom,284
    62. [LVGL] Image RGB zoom + opa,[LVGL] 253
    63. [LVGL] Image RGB zoom anti aliased,220
    64. [LVGL] Image RGB zoom anti aliased + opa,[LVGL] 196
    65. [LVGL] Image ARGB zoom,276
    66. [LVGL] Image ARGB zoom + opa,[LVGL] 267
    67. [LVGL] Image ARGB zoom anti aliased,196
    68. [LVGL] Image ARGB zoom anti aliased + opa,[LVGL] 190
    69. [LVGL] Text small,49
    70. [LVGL] Text small + opa,[LVGL] 51
    71. [LVGL] Text medium,48
    72. [LVGL] Text medium + opa,[LVGL] 50
    73. [LVGL] Text large,49
    74. [LVGL] Text large + opa,[LVGL] 50
    75. [LVGL] Text small compressed,39
    76. [LVGL] Text small compressed + opa,[LVGL] 40
    77. [LVGL] Text medium compressed,38
    78. [LVGL] Text medium compressed + opa,[LVGL] 37
    79. [LVGL] Text large compressed,32
    80. [LVGL] Text large compressed + opa,[LVGL] 33
    81. [LVGL] Line,99
    82. [LVGL] Line + opa,[LVGL] 100
    83. [LVGL] Arc think,87
    84. [LVGL] Arc think + opa,[LVGL] 87
    85. [LVGL] Arc thick,87
    86. [LVGL] Arc thick + opa,[LVGL] 86
    87. [LVGL] Substr. rectangle,85
    88. [LVGL] Substr. rectangle + opa,[LVGL] 76
    89. [LVGL] Substr. border,86
    90. [LVGL] Substr. border + opa,[LVGL] 86
    91. [LVGL] Substr. shadow,44
    92. [LVGL] Substr. shadow + opa,[LVGL] 43
    93. [LVGL] Substr. image,288
    94. [LVGL] Substr. image + opa,[LVGL] 288
    95. [LVGL] Substr. line,78
    96. [LVGL] Substr. line + opa,[LVGL] 80
    97. [LVGL] Substr. arc,86
    98. [LVGL] Substr. arc + opa,[LVGL] 86
    99. [LVGL] Substr. text,38
    100. [LVGL] Substr. text + opa,[LVGL] 38

     

     四、引申出来的RAM分配问题

            下面贴一下官方的SDK中定义的分配方案，看的我脑袋大，有点看不懂能不能这样使用，或者是这样使用会不会出现冲突。(0x62020000的意思是使用chache访问，和直接访问0x2202000是一个意思，但是nocache_ram_memory区域必须使用0x22034000直接访问，不能使用cache访问）。

            1.M0的ram_memory区域，ram_memory  (!rx) : ORIGIN = 0x6202A000, LENGTH = 24K，也就是0x2202A000-0x2203000,但是LP内核的itcm_memory (rx)  : ORIGIN = 0x2202C000, LENGTH = 16K，也就是0x2202C000-0x2203000;

            2.LP内核区域的dtcm_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 16K和M0内核的ram_wifi  (wxa)   : ORIGIN = 0x22030000, LENGTH = 160K - __EM_SIZE冲突，虽然LP内核内部没有cache功能，但是也好奇怪为什么还会划分idata和ddata这两个区域。

            3.我自己曾经尝试过按照不冲突的RAM地址升序顺序和严格按照手册所写的itcm和dtcm大小进行内存划分，没有发现明显区别，coremark和lvgl都没有任何提升。看看后续如何理解这个问题和解决问题。

    1. LP-MEMORY
    2. {
    3.     fw_header_memory  (rx)  : ORIGIN = 0x58020000 - 0x1000, LENGTH = 4K
    4.     xip_memory  (rx)  : ORIGIN = 0x58020000, LENGTH = 1M
    5.     itcm_memory (rx)  : ORIGIN = 0x2202C000, LENGTH = 16K
    6.     dtcm_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 16K
    7.     nocache_ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 0K
    8.     ram_memory  (!rx) : ORIGIN = 0x22034000, LENGTH = 16K
    9.     xram_memory  (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
    10. }
    11.  
    12. M0-MEMORY
    13. {
    14.     fw_header_memory  (rx)  : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
    15.     xip_memory  (rx)  : ORIGIN = 0x58000000, LENGTH = 32M
    16.     ram_psram  (wxa)  : ORIGIN = 0x50000000, LENGTH = 64M
    17.     itcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 20K
    18.     dtcm_memory (rx)  : ORIGIN = 0x62025000, LENGTH = 4K
    19.     nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 16K
    20.     ram_memory  (!rx) : ORIGIN = 0x6202A000, LENGTH = 24K
    21.     ram_wifi  (wxa)   : ORIGIN = 0x22030000, LENGTH = 160K - __EM_SIZE
    22.     xram_memory  (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
    23. }
    24.  
    25. D0-MEMORY
    26. {
    27.     fw_header_memory  (rx)  : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
    28.     xip_memory  (rx)  : ORIGIN = 0x58000000, LENGTH = 32M
    29.     itcm_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 28K
    30.     dtcm_memory (rx)  : ORIGIN = 0x3eff7000, LENGTH = 4K
    31.     nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K
    32.     ram_memory  (!rx) : ORIGIN = 0x3eff8000, LENGTH = 32K + 32K
    33.     xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
    34. }

            还是希望官方能够多给点文档看啊，linux下的M1S_DOCK_SDK好像就有很多正常的功能寄存器，还有库文件，我看文件抬头都是博流写的，真的是无语了。

            后续还是在Linux下使用M1S_DOCK_SDK开发吧，官方的库我实在是搞不懂。浪费精力。

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  • 原文地址：https://blog.csdn.net/DINGDING_GO/article/details/133562696