参考文献:
1,verilog 中 wire 和reg 的使用
2,解决一个assign问题,assign怎么用,assign有啥物理意义
wire和reg的区别:
input clk;
wire [1:0] a;
reg [1:0] b;
reg [1:0] c;
wire [3:0] out;
assign out = b; // reg 类型赋值给 assign
assign out = a; // wire类型赋值给 assign
assign out = b + c; // 寄存器类型相加,赋值给 assign
assign out = {a, b, c}; // 拼接的左边可以是 wire或reg。
// 寄存器类型被赋值,必须是 <=
always@(posedge clk) begin
b <= a;
end
案例
module a(
clk,
a,
b,
y,
out
);
input clk;
input a, b;
output wire y;
output reg out;
reg c, d;
always@(posedge clk)
begin
c <= a;
d <= b;
end
assign y = c + d;
always@(posedge clk)
begin
out <= y;
end
endmodule