ARM MPcore系统中ACP（加速器一致性接口的 ）作用 - 极术社区 - 连接开发者与智能计算生态
What is ACP?
Most of ARM's MPCore processors include an ACP, or Accelerator Coherency Port. ACPs are just AXI slave ports. You can connect an AXI master to the port, and the transactions generated by that master will pass through the MPCore processor in order to reach the main memory system.
Why?
This is a way of taking a non-cache coherent master and making it cache coherent.
As the master's transactions pass through the processor, they are visible to the coherency logic in the processor. This means that should they access an address held in the processor's caches, it can take the necessary steps to ensure coherency. Exactly how this works is down to the specific MPCore processor.
Note: In practice, it would have to be a non-cached master. As the ACP only gives visibility of the bus transactions, not any up-stream caches.
Who initiates transactions over ACP?
The master (the thing you connected to the ACP). From its perspective not much has changed.
什么是ACP？
ARM的大多数MPCore处理器都包含ACP或加速器相干端口。ACP只是AXI从端口。您可以将AXI主机连接到端口，该主机生成的事务将通过MPCore处理器到达主内存系统。
为什么？
这是一种获取非缓存一致性主机并使其缓存一致性的方法。
当主事务通过处理器时，它们对处理器中的一致性逻辑是可见的。这意味着，如果他们访问处理器缓存中保存的地址，它可以采取必要的步骤来确保一致性。具体的工作方式取决于特定的MPCore处理器。
注意：实际上，它必须是一个非缓存的主机。由于ACP只提供总线事务的可见性，而不提供任何上游缓存。
谁通过ACP发起交易？
主设备（您连接到ACP的设备）。从它的角度来看，变化不大。