• Design Compiler工具学习笔记（7）

    目录

    引言

    背景知识

    多时钟设计

    DC 输出文件分析

    实际操作

    设计源码

    综合脚本

    综合网表

    SDF文件

    SDC文件

    REPORT文件

    引言

    本篇继续学习 DC的基本使用。本篇主要学习 DC 综合之后的效果分析，多同步时钟设计以及 DC 综合完成之后的各种输出文件。

    前文链接：

    Design Compiler工具学习笔记（1）

    Design Compiler工具学习笔记（2）

    Design Compiler工具学习笔记（3）

    Design Compiler工具学习笔记（4）

    Design Compiler工具学习笔记（5）

    Design Compiler工具学习笔记（6）

    背景知识

    多时钟设计

    多周期约束时，对应的设计代码也需要修改。比如使能信号、数据有效信号需要延迟相应的时间。 

    DC 输出文件分析

     

     

    实际操作

    设计源码

    简单的设计文件：做一个9级延迟的寄存器链。源代码：

    1.  
    2. module MY_DESIGN 
    3. (
    4.   input I_CLK_100M,
    5.   input I_RSTN_100M,
    6.  
    7.   input I_DATA,
    8.   input I_VAL,
    9.  
    10.   output O_DATA
    11.   );
    12.  
    13. reg [9:0] R_I_DATA;
    14. genvar GV_I;
    15. generate
    16.   for(GV_I = 0;GV_I < 10;GV_I = GV_I + 1)
    17.   begin
    18.     always @ (posedge I_CLK_100M)
    19.     begin
    20.         if(~I_RSTN_100M)
    21.         begin
    22.           R_I_DATA[GV_I] <= 0;
    23.         end
    24.         else if(GV_I == 0)
    25.         begin
    26.           R_I_DATA[GV_I] <= I_DATA & I_VAL;
    27.         end
    28.         else
    29.         begin
    30.           R_I_DATA[GV_I] <= R_I_DATA[GV_I-1];
    31.         end
    32.     end
    33.   end
    34. endgenerate
    35.  
    36. assign O_DATA = R_I_DATA[9];
    37.  
    38. endmodule
    39.  
    40.  
    41.  
    42.  
    43.

    综合脚本

    1. # |===========================================================
    2. # | Author 		: Xu Y. B.
    3. # | Date   		: 2022-11-21
    4. # | Description : tcl script for top design 
    5. # |===========================================================
    6.  
    7.  
    8. # |===========================================================
    9. # |STEP 1: Read & elaborate the RTL design file list & check
    10. # |===========================================================
    11. set TOP_MODULE MY_DESIGN
    12. analyze        -format verilog [list MY_DESIGN.v]
    13. elaborate      $TOP_MODULE     -architecture verilog
    14. current_design $TOP_MODULE
    15.  
    16. if {[link] == 0} {
    17. 	echo "Your Link has errors !";
    18. 	exit;
    19. }
    20.  
    21. if {[check_design] == 0} {
    22. 	echo "Your check design has errors !";
    23. 	exit;
    24. }
    25.  
    26. # |===========================================================
    27. # |STEP 2: reset design
    28. # |===========================================================
    29. reset_design
    30.  
    31.  
    32. # |===========================================================
    33. # |STEP 3: Write unmapped ddc file
    34. # |===========================================================
    35. uniquify
    36. set uniquify_naming_style "%s_%d"
    37. write -f ddc -hierarchy -output ${UNMAPPED_PATH}/${TOP_MODULE}.ddc
    38.  
    39.  
    40. # |===========================================================
    41. # |STEP 4: define clocks
    42. # |===========================================================
    43. # -------------------------- CLK 100MHz ----------------------
    44. set       CLK_NAME          	I_CLK_100M
    45. set       CLK_PERIOD        	10
    46. set       CLK_SKEW	        	[expr {$CLK_PERIOD*0.05}]						
    47. set       CLK_TRANS         	[expr {$CLK_PERIOD*0.01}]						
    48. set       CLK_SRC_LATENCY   	[expr {$CLK_PERIOD*0.1 }]						
    49. set       CLK_LATENCY       	[expr {$CLK_PERIOD*0.1 }]						
    50.  
    51. create_clock 			-period 	$CLK_PERIOD  	  [get_ports $CLK_NAME]
    52. set_ideal_network 						 			  [get_ports $CLK_NAME]
    53. set_dont_touch_network 					 			  [get_ports $CLK_NAME]
    54. set_drive 				0 							  [get_ports $CLK_NAME]
    55.  
    56. set_clock_uncertainty   -setup       $CLK_SKEW        [get_clocks $CLK_NAME]
    57. set_clock_transition    -max         $CLK_TRANS       [get_clocks $CLK_NAME]
    58. set_clock_latency       -source -max $CLK_SRC_LATENCY [get_clocks $CLK_NAME]
    59. set_clock_latency       -max         $CLK_LATENCY     [get_clocks $CLK_NAME]
    60.  
    61. # --------------------------- CLK 50MHz ----------------------
    62. # set       CLK_NAME_2          	I_CLK_50M
    63. # set       CLK_PERIOD_2        	20
    64. # set       CLK_SKEW_2	        [expr {$CLK_PERIOD_2*0.05}]						
    65. # set       CLK_TRANS_2         	[expr {$CLK_PERIOD_2*0.01}]						
    66. # set       CLK_SRC_LATENCY_2   	[expr {$CLK_PERIOD_2*0.1 }]						
    67. # set       CLK_LATENCY_2       	[expr {$CLK_PERIOD_2*0.1 }]						
    68.  
    69. # create_clock 			-period 	$CLK_PERIOD_2  	  [get_ports $CLK_NAME_2]
    70. # set_ideal_network 						 			  [get_ports $CLK_NAME_2]
    71. # set_dont_touch_network 					 			  [get_ports $CLK_NAME_2]
    72. # set_drive 				0 							  [get_ports $CLK_NAME_2]
    73.  
    74. # set_clock_uncertainty   -setup       $CLK_SKEW_2        [get_clocks $CLK_NAME_2]
    75. # set_clock_transition    -max         $CLK_TRANS_2       [get_clocks $CLK_NAME_2]
    76. # set_clock_latency       -source -max $CLK_SRC_LATENCY_2 [get_clocks $CLK_NAME_2]
    77. # set_clock_latency       -max         $CLK_LATENCY_2     [get_clocks $CLK_NAME_2]
    78.  
    79.  
    80. # |===========================================================
    81. # |STEP 5: define reset
    82. # |===========================================================
    83. # ------------------------- RST 1 ----------------------------
    84. set RST_NAME 					I_RSTN_100M
    85. set_ideal_network 				[get_ports $RST_NAME]
    86. set_dont_touch_network          [get_ports $RST_NAME]
    87. set_drive             0         [get_ports $RST_NAME]
    88.  
    89. # # ------------------------- RST 2 ----------------------------
    90. # set RST_NAME_2 					I_RSTN_50M
    91. # set_ideal_network 				[get_ports $RST_NAME_2]
    92. # set_dont_touch_network          [get_ports $RST_NAME_2]
    93. # set_drive             0         [get_ports $RST_NAME_2]
    94.  
    95.  
    96. # |===========================================================
    97. # |STEP 6: set input delay using timing budget
    98. # |Assume a weak cell to drive the input pins
    99. # |===========================================================
    100. set 		LIB_NAME 			typical
    101. set 		WIRE_LOAD_MODEL 	smic18_wl10
    102.  
    103.  
    104. set 		DRIVE_PIN 			Y
    105. set 		OPERATE_CONDITION   typical
    106.  
    107. set 		ALL_INPUT_EXCEPT_CLK [remove_from_collection [all_inputs] [get_ports "$CLK_NAME"]]
    108. set         INPUT_DELAY 		 [expr {$CLK_PERIOD*0.6}]
    109.  
    110. set_input_delay  $INPUT_DELAY -clock         $CLK_NAME         $ALL_INPUT_EXCEPT_CLK
    111. set_driving_cell -lib_cell    ${DRIVE_CELL}  -pin ${DRIVE_PIN} $ALL_INPUT_EXCEPT_CLK
    112.  
    113.  
    114.  
    115. # |===========================================================
    116. # |STEP 7: set output delay 
    117. # |===========================================================
    118. set OUTPUT_DELAY  [expr {$CLK_PERIOD*0.6}]
    119. set MAX_LOAD      [expr {[load_of $LIB_NAME/INVX4/A] * 10}]
    120.  
    121. set_output_delay  $OUTPUT_DELAY -clock $CLK_NAME 	 [all_outputs]
    122. set_load 		  [expr {$MAX_LOAD * 3}] 			 [all_outputs]
    123. set_isolate_ports -type buffer 					 	 [all_outputs]
    124.  
    125.  
    126. # |===========================================================
    127. # |STEP 8: set max delay for comb logic 
    128. # |===========================================================
    129. # set_input_delay  [expr $CLK_PERIOD * 0.1] -clock $CLK_NAME -add_delay [get_ports I_1]
    130. # set_output_delay [expr $CLK_PERIOD * 0.1] -clock $CLK_NAME -add_delay [get_ports O_1]
    131.  
    132.  
    133. # |===========================================================
    134. # |STEP 9: set operating condition & wire load model 
    135. # |===========================================================
    136. set_operating_conditions -max 			$OPERATE_CONDITION \
    137. 						 -max_library 	$LIB_NAME
    138.  
    139. set 					 auto_wire_load_selection false
    140. set_wire_load_mode  	 top
    141. set_wire_load_model		 -name    $WIRE_LOAD_MODEL \
    142. 						 -library $LIB_NAME
    143.  
    144.  
    145. # |===========================================================
    146. # |STEP 10: set area constraint (Let DC try its best) 
    147. # |===========================================================
    148. set_max_area			 1000
    149.  
    150.  
    151. # |===========================================================
    152. # |STEP 11: set DRC constraint 
    153. # |===========================================================
    154. # set MAX_CAPACITANCE [expr {[load_of $LIB_NAME/NAND4X2/Y] * 5}]
    155. # set_max_capacitance $MAX_CAPACITANCE $ALL_INPUT_EXCEPT_CLK
    156.  
    157.  
    158. # |===========================================================
    159. # |STEP 12: set group path
    160. # |Avoid getting stack on one path
    161. # |===========================================================
    162. group_path -name $CLK_NAME -weight 5 				\
    163. 						   -critical_range  [expr {$CLK_PERIOD * 0.1}] 
    164.  
    165. group_path -name INPUTS    -from [all_inputs] 		\
    166. 					 	   -critical_range  [expr {$CLK_PERIOD * 0.1}] 
    167.  
    168. group_path -name OUTPUTS   -to [all_outputs] 		\
    169. 						   -critical_range  [expr {$CLK_PERIOD * 0.1}] 
    170.  
    171. group_path -name COMBS     -from [all_inputs] 		\
    172. 						   -to [all_outputs] 		\
    173. 						   -critical_range  [expr {$CLK_PERIOD * 0.1}] 	
    174. report_path_group
    175.  
    176.  
    177. # |===========================================================
    178. # |STEP 13: Elimate the multiple-port inter-connect &
    179. # |			define name style
    180. # |===========================================================
    181. # set_app_var 						verilogout_no_tri 					true
    182. # set_app_var						verilogout_show_unconnected_pins 	true
    183. # set_app_var						bus_naming_style					{%s[%d]}
    184. # simplify_constants 				-boundary_optimization
    185. # set_boundary_optimization 		[current_design] 					true
    186. # set_fix_multiple_port_nets 		-all 								-buffer_constants
    187.  
    188.  
    189. # |===========================================================
    190. # |STEP 14: timing exception define
    191. # |===========================================================
    192. # set_false_path -from [get_clocks I_CLK_100M] -to [get_clocks I_CLK_100M]
    193. # set ALL_CLKS [all_clocks]
    194. # foreach_in_collection CUR_CLK $ALL_CLKS 
    195. # {
    196. # 	set OTHER_CLKS [remove_from_collection [all_clocks] $CUR_CLK]
    197. # 	set_false_path -from $CUR_CLK $OTHER_CLKS
    198. # }
    199.  
    200. # set_false_path -from [get_clocks I_CLK_100M] -to [get_clocks I_CLK_100M]
    201. # set_false_path -from [get_clocks I_CLK_100M] -to [get_clocks I_CLK_100M]
    202.  
    203. # set_disable_timing TOP/U1 -from a -to y
    204. # set_case_analysis 0 [get_ports sel_i]
    205.  
    206. # set_multicycle_path -setup 6 -from FFA/CP -through ADD/out -to FFB/D
    207. # set_multicycle_path -hold 5 -from FFA/CP -through ADD/out -to FFB/D
    208. # set_multicycle_path -setup 2 -to FFB/D
    209. # set_multicycle_path -hold 1 -to FFB/D
    210.  
    211.  
    212.  
    213. # |===========================================================
    214. # |STEP 15: compile flow
    215. # |===========================================================
    216. # ungroup -flatten -all
    217.  
    218. # 1st-pass compile
    219. # compile -map_effort high -area_effort high
    220. # compile -map_effort high -area_effort high -boundary_optimization
    221. compile -map_effort high  -area_effort high
    222.  
    223. # simplify_constants -boundary_optimization
    224. # set_fix_multiple_port_nets -all -buffer_constants
    225.  
    226. # compile -map_effort high -area_effort high -incremental_mapping -scan
    227.  
    228. # 2nd-pass compile
    229. # compile -map_effort high -area_effort high -incremental_mapping -boundary_optimization
    230. # compile_ultra -incr
    231.  
    232.  
    233. # |===========================================================
    234. # |STEP 16: write post-process files
    235. # |===========================================================
    236. change_names -rules verilog -hierarchy
    237. remove-unconnected_ports [get_cells -hier *] -blast_buses
    238. # Write the mapped files
    239. write -f ddc -output $MAPPED_PATH/${TOP_MODULE}.ddc
    240. write 	-f verilog 	-hierarchy -output 	$MAPPED_PATH/${TOP_MODULE}.v
    241. write_sdc -version 	1.7 				$MAPPED_PATH/${TOP_MODULE}.sdc
    242. write_sdf -version 	2.1 				$MAPPED_PATH/${TOP_MODULE}.sdf
    243.  
    244. # |===========================================================
    245. # |STEP 17: generate report files
    246. # |===========================================================
    247. # Get report file
    248. redirect   -tee     -file     ${REPORT_PATH}/check_design.txt 			{check_design}
    249. redirect   -tee     -file     ${REPORT_PATH}/check_timing.txt 			{check_timing}
    250. redirect   -tee     -file     ${REPORT_PATH}/report_constraint.txt 		{report_constraint -all_violators}
    251. redirect   -tee     -file     ${REPORT_PATH}/check_setup.txt 			{report_timing -delay_type max}
    252. redirect   -tee     -file     ${REPORT_PATH}/check_hold.txt 			{report_timing -delay_type min}
    253. redirect   -tee     -file     ${REPORT_PATH}/report_area.txt 			{report_area}

    综合网表

    打开映射后的 .v 文件：

    编译时可以加上 -scan 选项，观察寄存器映射的差别：

    SDF文件

    里面包含了单元的延迟信息。

    SDC文件

    里面包含了该设计的所有约束

    REPORT文件

    可以分别打开进行分析，包括时间、面积等。此处就不一一展开。

     

    至此 DC 的视频学习告一段落，了解了基本的使用技巧。但是功夫还需要磨练，多结合工程进行实践是必不可缺的环节。继续加油~~

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  • 原文地址：https://blog.csdn.net/qq_43045275/article/details/128041162