| 作者 | 将狼才鲸 |
|---|---|
| 创建日期 | 2022-11-06 |
Cortex-M3不使用ARM指令集,而是使用Thumb或者Thumb-2指令集。
M3共有116条指令(不是指令码的数量,一条指令会有多条指令码与之对应)。
指令集ARM官网在线阅读地址为Processor instructions。
在M3用户手册ARM Cortex-M3 Processor Technical Reference Manual的表3-1中也有同样的描述。
| Operation | Description | Assembler | Cycles |
|---|---|---|---|
| Move | Register | MOV Rd, | 1 |
| 16-bit immediate | MOVW Rd, # | 1 | |
| Immediate into top | MOVT Rd, # | 1 | |
| To PC | MOV PC, Rm | 1 + P | |
| Add | Add | ADD Rd, Rn, | 1 |
| Add to PC | ADD PC, PC, Rm | 1 + P | |
| Add with carry | ADC Rd, Rn, | 1 | |
| Form address | ADR Rd, | 1 | |
| Subtract | Subtract | SUB Rd, Rn, | 1 |
| Subtract with borrow | SBC Rd, Rn, | 1 | |
| Reverse | RSB Rd, Rn, | 1 | |
| Multiply | Multiply | MUL Rd, Rn, Rm | 1 |
| Multiply accumulate | MLA Rd, Rn, Rm | 2 | |
| Multiply subtract | MLS Rd, Rn, Rm | 2 | |
| Long signed | SMULL RdLo, RdHi, Rn, Rm | 3 to 5 | |
| Long unsigned | UMULL RdLo, RdHi, Rn, Rm | 3 to 5 | |
| Long signed accumulate | SMLAL RdLo, RdHi, Rn, Rm | 4 to 7 | |
| Long unsigned accumulate | UMLAL RdLo, RdHi, Rn, Rm | 4 to 7 | |
| Divide | Signed | SDIV Rd, Rn, Rm | |
| Unsigned | UDIV Rd, Rn, Rm | 2 to 12 | |
| Saturate | Signed | SSAT Rd, #, | |
| Unsigned | USAT Rd, #, | 1 | |
| Compare | Compare | CMP Rn, | 1 |
| Negative | CMN Rn, | 1 | |
| Logical | AND | AND Rd, Rn, | 1 |
| Exclusive OR | EOR Rd, Rn, | 1 | |
| OR | ORR Rd, Rn, | 1 | |
| OR NOT | ORN Rd, Rn, | 1 | |
| Bit clear | BIC Rd, Rn, | 1 | |
| Move NOT | MVN Rd, | 1 | |
| AND test | TST Rn, | 1 | |
| Exclusive OR test | TEQ Rn, | ||
| Shift | Logical shift left | LSL Rd, Rn, # | 1 |
| Logical shift left | LSL Rd, Rn, Rs | 1 | |
| Logical shift right | LSR Rd, Rn, # | 1 | |
| Logical shift right | LSR Rd, Rn, Rs | 1 | |
| Arithmetic shift right | ASR Rd, Rn, # | 1 | |
| Arithmetic shift right | ASR Rd, Rn, Rs | 1 | |
| Rotate | Rotate right | ROR Rd, Rn, # | 1 |
| Rotate right | ROR Rd, Rn, Rs | 1 | |
| With extension | RRX Rd, Rn | 1 | |
| Count | Leading zeroes | CLZ Rd, Rn | 1 |
| Load | Word | LDR Rd, [Rn, ] | 2 |
| To PC | LDR PC, [Rn, ] | 2 + P | |
| Halfword | LDRH Rd, [Rn, ] | 2 | |
| Byte | LDRB Rd, [Rn, ] | 2 | |
| Signed halfword | LDRSH Rd, [Rn, ] | 2 | |
| Signed byte | LDRSB Rd, [Rn, ] | 2 | |
| User word | LDRT Rd, [Rn, #] | 2 | |
| User halfword | LDRHT Rd, [Rn, #] | 2 | |
| User byte | LDRBT Rd, [Rn, #] | 2 | |
| User signed halfword | LDRSHT Rd, [Rn, #] | 2 | |
| User signed byte | LDRSBT Rd, [Rn, #] | 2 | |
| PC relative | LDR Rd,[PC, #] | 2 | |
| Doubleword | LDRD Rd, Rd, [Rn, #] | 1 + N | |
| Multiple | LDM Rn, {} | 1 + N | |
| Multiple including PC | LDM Rn, {, PC} | 1 + N + P | |
| Store | Word | STR Rd, [Rn, ] | 2 |
| Halfword | STRH Rd, [Rn, ] | 2 | |
| Byte | STRB Rd, [Rn, ] | 2 | |
| Signed halfword | STRSH Rd, [Rn, ] | 2 | |
| Signed byte | STRSB Rd, [Rn, ] | 2 | |
| User word | STRT Rd, [Rn, #] | 2 | |
| User halfword | STRHT Rd, [Rn, #] | 2 | |
| User byte | STRBT Rd, [Rn, #] | 2 | |
| User signed halfword | STRSHT Rd, [Rn, #] | 2 | |
| User signed byte | STRSBT Rd, [Rn, #] | 2 | |
| Doubleword | STRD Rd, Rd, [Rn, #] | 1 + N | |
| Multiple | STM Rn, {} | 1 + N | |
| Push | Push | PUSH {} | |
| Push with link register | PUSH {, LR} | 1 + N | |
| Pop | Pop | POP {} | |
| Pop and return | POP {, PC} | 1 + N + P | |
| Semaphore | Load exclusive | LDREX Rd, [Rn, #] | 2 |
| Load exclusive half | LDREXH Rd, [Rn] | 2 | |
| Load exclusive byte | LDREXB Rd, [Rn] | 2 | |
| Store exclusive | STREX Rd, Rt, [Rn, #] | 2 | |
| Store exclusive half | STREXH Rd, Rt, [Rn] | 2 | |
| Store exclusive byte | STREXB Rd, Rt, [Rn] | 2 | |
| Clear exclusive monitor | CLREX | 1 | |
| Branch | Conditional | B | 1 or 1 + P |
| Unconditional | B | 1 + P | |
| With link | BL | 1 + P | |
| With exchange | BX Rm | 1 + P | |
| With link and exchange | BLX Rm | 1 + P | |
| Branch if zero | CBZ Rn, | 1 or 1 + P | |
| Branch if non-zero | CBNZ Rn, | 1 or 1 + P | |
| Byte table branch | TBB [Rn, Rm] | 2 + P | |
| Halfword table branch | TBH [Rn, Rm, LSL#1] | 2 + P | |
| State change | Supervisor call | SVC # | - |
| I | f-then-else | IT… | 1 |
| Disable interrupts | CPSID | 1 or 2 | |
| Enable interrupts | CPSIE | 1 or 2 | |
| Read special register | MRS Rd, | 1 or 2 | |
| Write special register | MSR , Rn | 1 or 2 | |
| Breakpoint | BKPT # | - | |
| Extend | Signed halfword to word | SXTH Rd, | 1 |
| Signed byte to word | SXTB Rd, | 1 | |
| Unsigned halfword | UXTH Rd, | 1 | |
| Unsigned byte | UXTB Rd, | 1 | |
| Bit field | Extract unsigned | UBFX Rd, Rn, #, # | 1 |
| Extract signed | SBFX Rd, Rn, #, # | 1 | |
| Clear | BFC Rd, Rn, #, # | 1 | |
| Insert | BFI Rd, Rn, #, # | 1 | |
| Reverse | Bytes in word | REV Rd, Rm | 1 |
| Bytes in both halfwords | REV16 Rd, Rm | 1 | |
| Signed bottom halfword | REVSH Rd, Rm | 1 | |
| Bits in word | RBIT Rd, Rm | 1 | |
| Hint | Send event | SEV | 1 |
| Wait for event | WFE | 1 + W | |
| Wait for interrupt | WFI | 1 + W | |
| No operation | NOP | 1 | |
| Barriers | Instruction synchronization | ISB | 1 + B |
| Data memory | DMB | 1 + B | |
| Data synchronization | DSB | 1 + B |