目录
armv7 芯片手册：
Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just
below the address in SP, and updates SP to point to the start of the stored data.
Assembler syntax
PUSH{
}{ }Standard syntax
STMDB{}{ } SP!,Equivalent STM syntax
where:
, See Standard assembler syntax fields on page A8-285.Is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also Encoding of lists of ARM core registers on page A8-292.
If the list contains more than one register, the instruction is assembled to encoding T1, T2, or A1. If the list contains exactly one register, the instruction is assembled to encoding T1, T3, or A2. The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. However:
• ARM deprecates the use of ARM instructions that include the PC in the list
• if the SP is in the list, and it is not the lowest-numbered register in the list, the instruction
stores an UNKNOWN value for the SP.
push支持同时将多个寄存器入栈，格式：{xx,xx}，如：push {r0, r1,r2}
Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data.
POP{
}{ }Standard syntax
LDM{}{ } SP!,Equivalent LDM syntax
Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address
如同push一样，pop也支持同时pop出栈多个寄存器
Branch causes a branch to a target address.
B{
}{ }
Branch with Link calls a subroutine at a PC-relative address.
Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM.
BL{X}{
}{ }The label of the instruction that is to be branched to.
For BL (encodings T1, A1), the assembler calculates the required value of the offset from the PC value of the BL instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –16777216 to 16777214 (Thumb) or multiples of 4 in the range –33554432 to 33554428 (ARM).
BL指令于B指令区别：
BL函数条跳转前执行：LR = PC - 4; （armv7为例）
Note: bl指令会计算label和当前pc位置的offset，所以这是相对跳转
Branch and Exchange causes a branch to an address and instruction set specified by a register.
BX{
}{ }The register that contains the branch target address and instruction set selection bit. The PC can be used. This register can be the SP in both ARM and Thumb instructions, but ARM deprecates this use of the SP.